Multiple faults: Modeling, simulation and test

Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002

Volumn , Issue , 2002, Pages 592-597

  Kim, Yong Chang ^a,b   Agrawal, V D ^a   Saluja, K K ^a  

^a UNIVERSITY OF WISCONSIN MADISON   (United States)

^b AGERE SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMBINATORIAL CIRCUITS; COMPUTER AIDED DESIGN; DESIGN; INTEGRATED CIRCUIT TESTING; RECONFIGURABLE HARDWARE;

BRIDGING FAULT; CIRCUIT OPTIMIZATION; MODELING TECHNIQUE; MULTIPLE FAULTS; PARTIAL SCAN CIRCUITS; SINGLE STUCK-AT FAULTS; STUCK-AT FAULTS; TEST GENERATIONS;

VLSI CIRCUITS;

EID: 84962303677     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2002.995000     Document Type: Conference Paper

References (21)

1. E. M. Aboulhamid, Y. Karkouri, and E. Cerny, "On the Generation of Test Patterns for Multiple Faults," J. Electronic Testing: Theory and Applic., vol. 4, no. 3, pp. 237-253, Aug. 1993.
2. M. Abramovici, M. A. Breuer, and A. D. Friedman, Digital Systems Testing and Testable Design. New York: IEEE Press, 1990.
3. V. K. Agarwal and A. S. F. Fung, "Multiple Fault Testing of Large Circuits by Single Fault Test Sets," IEEE Trans. Computers, vol. C-30, no. 11, pp. 855-865, Nov. 1981.
4. P. Agrawal, V. D. Agrawal, and S. C. Seth, "Generating Tests for Delay Faults in Nonscan Circuits," IEEE Design & Test of Computers, vol. 10, pp. 20-28, Mar. 1993.
5. D. C. Bossen and S. J. Hong, "Cause-Effect Analysis for Multiple Fault Detection in Combinational Networks," IEEE Trans. Computers, vol. C-20, no. 11, pp. 1252-1257, Nov. 1971.
6. M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory & Mixed-Signal VLSI Circuits. Boston: Kluwer Academic Publishers, 2000.
7. H. Y. Chang, E. G. Manning, and G. Metze, Fault Diagnosis of Digital Systems. New York: Wiley-Interscience, 1970.
8. K.-T. Cheng and V. D. Agrawal, "A Partial Scan Method for Sequential Circuits with Feedback," IEEE Trans. Computers, vol. 39, no. 4, pp. 544-548, Apr. 1990.
9. W. T. Cheng and T. J. Chakraborty, "GENTEST: An Automatic Test Generation System for Sequential Circuits," Computer, vol. 22, no. 4, pp. 43-49, Apr. 1989.
10. D. L. Dietmeyer, Logic Design of Digital Systems. Boston: Allyn and Bacon, third edition, 1988.
11. J. P. Hayes, "A NAND Model for Fault Diagnosis in Combinational Logic Networks," IEEE Trans. Computers, vol. C-20, no. 12, pp. 1496-1506, Dec. 1971.
12. D. A. Huffman, "Combinational circuits with feedback," in A. Mukhopadhyay, editor, Recent Deveolpments in Switching Theory, New York: Academic press, 1971.
13. J. L. A. Hughes and E. J. McCluskey, "Multiple Stuck-at Fault Coverage of Single Stuck-at Fault Test Sets," in Proc. Int. Test Conf., Sept. 1986, pp. 368-374.
14. J. Jacob and N. N. Biswas, "GTBD Faults and Lower Bounds on Multiple Fault Coverage of Single Fault Test Sets," in Proc. Int. Test Conf., Sept. 1988, pp. 849-855.
15. Y. C. Kim, V. D. Agrawal, and K. K. Saluja, "Combinational Test Generation for Acyclic Sequential Circuits using a Balanced ATPG Model,"in Proc. 14th Int. Conf. on VLSI Design, Jan. 2001, pp. 143-148.
16. Y. C. Kim, V. D. Agrawal, and K. K. Saluja, "Combinational Test Generation for Various Clases of Acyclic Sequential Circuits,"in Proc. Int. Test Conf., Oct. 2001.
17. I. Kohavi and Z. Kohavi, "Detection of Multiple Faults in Combinational Logic Networks," IEEE Trans. Computers, vol. C-21, no. 6, pp. 556-568, June 1972.
18. P. Muth, "A Nine-Value Circuit Model for Test Generation," IEEE Trans. Computers, vol. C-25, no. 6, pp. 630-636, June 1976.
19. D. R. Schertz and G. Metze, "A New Representation of Faults in Combinational Digital Circuits," IEEE Trans. Computers, vol. C-21, no. 8, pp. 858-866, Aug. 1972.
20. W. R. Simpson and J. W. Sheppard, System Test and Diagnosis. Boston: Kluwer Academic Publishers, 1994.
21. Synopsys, Inc., 700 East Middlefield Rd., Mountain View, CA 94043, TetraMAX ATPG User Guide, v2000.11 edition, November 2000. Document Order Number: 37043-000 TBD.