An all-digital DFT scheme for testing catastropic faults in PLLs

IEEE Design and Test of Computers

Volumn 20, Issue 1, 2003, Pages 60-67

  Azaïs, Florence ^a   Bertrand, Yves ^d   Renovell, Michel ^d   Ivanov, André ^b   Tabatabaei, Sassan ^c  

^a LIRMM   (France)

^b UNIVERSITY OF BRITISH COLUMBIA   (Canada)

^c Vector 12 Corp   (Canada)

^d NONE

Author keywords

[No Author keywords available]

Indexed keywords

DISCRETE FOURIER TRANSFORMS; ELECTRONIC EQUIPMENT TESTING; INTEGRATED CIRCUITS; VARIABLE FREQUENCY OSCILLATORS;

CATASTROPHIC FAULTS;

PHASE LOCKED LOOPS;

EID: 0037246492     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2003.1173054     Document Type: Article

References (12)

1. K.D. Wagner and T.W. Williams, "Design for Testability of Mixed Signal Integrated Circuits," Proc. Int'l Test Conf. (ITC 88), IEEE CS Press, Los Alamitos, Calif., 1988, pp. 823-829.
2. M. Soma, "A Design-for-Test Methodology for Active Analog Filters," Proc. Int'l Test Conf. (ITC 90), IEEE CS Press, Los Alamitos, Calif., 1990, pp. 183-192.
3. J.L. Huertas, A. Rueda, and D. Vazquez, "Testable Switched-Capacitor Filters," IEEE J. Solid State Circuits, vol. 28, no. 7, July 1993, pp. 719-724.
4. K. Arabi and B. Kaminska, "Oscillation-Test Strategy for Analog and Mixed-Signal Integrated Circuits," Proc. VLSI Test Symp. (VTS 96), IEEE CS Press, Los Alamitos, Calif., 1996, pp. 476-482.
5. M. Renovell, F. Azaïs, and Y. Bertrand, "The Multi-Configuration: A DFT Technique for Analog Circuits," Proc. VLSI Test Symp. (VTS 96), IEEE CS Press, Los Alamitos, Calif., 1996, pp. 54-59.
6. R.E. Best, Phase-Locked Loops: Theory, Design and Applications, 2nd ed., MCGraw-Hill, New York, 1993.
7. B.R. Veilette and G.W. Roberts, "On-Chip Measurement of the Transfer Function of Charge-Pump Phase-Locked Loops," Proc. Int'l Test Conf. (ITC 97), IEEE Press, Piscataway, N.J., 1997, pp. 776-785.
8. P. Goteti, G. Devarayanadurg, and M. Soma, "DFT for Embedded Charge-Pump PLL Systems Incorporating IEEE 1149.1, " Proc. Custom Integrated Circuits Conf., IEEE Press, Piscataway, N.J., 1997, pp. 210-213.
9. S. Sunter and A. Roy, "BIST for Phase-Locked Loops in Digital Applications," Proc. Int'l Test Conf. (ITC 99), IEEE Press, Piscataway, N.J., 1999, pp. 532-540.
10. R. Stoffels, "Cost Effective Frequency Measurement for Production Testing: New Approaches on PLL Testing," Proc. Int'l Test Conf. (ITC 96), IEEE Press, Piscataway, N.J., 1996, pp. 708-716.
11. F. Azaïs et al., "A Methodology and Design for Effective Testing of Voltage-Controlled Oscillators," Proc. Asian Test Symp., IEEE CS Press, Los Alamitos, Calif., 1998, pp. 383-387.
12. J. Galiay, Y. Crouzet, and M. Verginault, "Physical Versus Logical Fault Models for MOS LSI Circuits: Impact on Their Testability," IEEE Trans. Computers, vol. 29, no. 6, June 1980, pp. 527-531.