PLL based high speed functional testing

Proceedings of the Asian Test Symposium

Volumn 2003-January, Issue , 2003, Pages 116-119

  Jayabalan, J ^a   Goh, Chee Kiang ^b   Leong, Ooi Ban ^a   Seng, Leong Mook ^a   Iyer, M K ^c   Tay, A A O ^a  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^b INFINEON TECHNOLOGIES AG   (Germany)

^c INSTITUTE OF MICROELECTRONICS   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCKS; INTEGRATED CIRCUIT TESTING; JITTER; TIMING JITTER;

AT-SPEED; CLOCK-JITTER; FUNCTIONAL TESTING; HIGH SPEED; JITTER TOLERANCE; SILICON DEVICES;

SPEED;

EID: 28444434994     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ATS.2003.1250794     Document Type: Conference Paper

References (6)

1. PLL based discrete time varying filter for estimation of parameters of a sine signal corrupted by a closely spaced FM interference Wulich, D. Plotkin, E.I. Swamy, M.N.S. Tong, W. Circuits and Systems, 1990., IEEE International Symposium pp: 771-774 vol.1
2. PLL-Based, Impedance Controlled Output Buffer Shirotori,T.;Nogami,K. VLSI Circuits,1991. Digest of Technical Papers. 1991 Symposium pp 49-50
3. Oscillatorless clock multiplication Aguiar R.L. Santos, D.M. Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium pp: 630-633 vol. 4
4. A dual PLL based multi frequency clock distribution scheme Thaik, A. Nguyen, H.N. VLSI Circuits, 1992. Digest of Technical Papers. Symposium on pp: 84-85
5. Cost effective frequency measurement for production testing: new approaches on PLL testing Stoffels, R.; Test Conference, 1996.Proceedings., International, Oct 1996 pp: 708-716
6. Parametric built-in self-test of VLSI systems Niggemeyer, D. Ruffer, M. Design, Automation and Test in Europe Conference and Exhibition 1999. Proceedings pp: 376-380