Design-for-test techniques for opens in undetected branches in CMOS latches and flip-flops

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 15, Issue 5, 2007, Pages 572-577

  Ramirez, Antonio Zenteno ^a   Espinosa, Guillermo ^b   Champac, Victor ^c  

^a INTEL CORPORATION   (United States)

^b FREESCALE SEMICONDUCTOR INC   (United States)

^c INSTITUTO NACIONAL DE ASTROFÍSICA   (Mexico)

Author keywords

Design for testability (DFT); Flip flops; Latches; Resistive opens; Undetected opens

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; FABRICATION; FLIP FLOP CIRCUITS; PARAMETER ESTIMATION; STATIC ANALYSIS;

ANALYTICAL ANALYSIS; CIRCUITS FABRICATION; RESISTIVE OPENS; UNDETECTED OPENS;

DESIGN FOR TESTABILITY;

EID: 34249792129     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2007.896910     Document Type: Article

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