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Volumn , Issue , 2004, Pages 216-221

Enhancing BIST based single/multiple stuck-at fault diagnosis by ambiguous test set

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; ELECTRIC FAULT CURRENTS; FAILURE ANALYSIS; INFORMATION ANALYSIS; NETWORKS (CIRCUITS); VECTORS;

EID: 13244265473     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (4)

References (15)
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  • 2
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    • Wu, Y.1    Adham, S.M.I.2
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    • Y. Wu and S. M. I. Adham, "Scan-Based BIST Fault Diagnosis," IEEE Trans. CAD, vol. 18, no.2, pp.203-211, 1999.
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  • 5
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    • Rajski, J.1    Tyszer, J.2
  • 7
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    • Savir, J.1    McAnney, W.H.2
  • 8
    • 0033336301 scopus 로고    scopus 로고
    • Fault diagnosis in scan-based BIST using both time and space information
    • J. G-Dastidar, D. Das and N. A. Touba, "Fault Diagnosis in Scan-Based BIST Using Both Time and Space Information," Proc. ITC, pp.95-102, 1999.
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  • 10
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    • On diagnosing multiple stuck-at faults using multiple and single fault simulation in combinational circuits
    • H. Takahashi, K. O. Boateng, K. K. Saluja and Y. Takamatsu, "On Diagnosing Multiple Stuck-at Faults using Multiple and Single Fault Simulation in Combinational Circuits," IEEE Trans. CAD, vol.21, no.3, pp.362-368, 2002.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.