Statistical test development for analog circuits under high process variations

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 26, Issue 8, 2007, Pages 1465-1477

  Liu, Fang ^a,b   Ozev, Sule ^a,b  

^a IEEE   (United States)

^b USA   (United States)

Author keywords

Analog test; Process variability; Test time reduction

Indexed keywords

ANALOG TEST; PROBABILISTIC DETECTION; PROCESS VARIABILITY; TEST TIME REDUCTION;

AUTOMATION; COMPUTER SIMULATION; NETWORKS (CIRCUITS); PARAMETER ESTIMATION; PROBABILITY; STATISTICAL TESTS;

ANALOG CIRCUITS;

EID: 34547157032     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2007.891373     Document Type: Article

References (36)

1. Semiconductor Industry Association, International Technology Roadmap for Semiconductors, 2005. [Online]. Available: http://www.itrs.net/ Common./2005ITRS/Home2005.htm
2. M. Soma, "An experimental approach to analog fault models," in Proc, IEEE Custom Integr. Circuits Conf, May 199.1, pp. 13.6/1-13.6/4.
3. L. Milor, "A tutorial introduction to research on analog and mixed-signal circuit testing," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 45, no. 10, pp. 1389-1407, Oct. 1998.
4. M. Soma, "Challenges in analog and mixed-signal fault models," IEEE Circuits Devices Mag., vol. 12, no. 1, pp. 1-13, Jan. 1996.
5. P. N. Variyam and A. Chatterjee, "Specification-driven test generation for analog circuits," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 19, no. 10, pp. 1189-1201, Oct. 2000.
6. R. Voorakaranam, S. Chakrabarti, J. Hou, A. Gomes, S. Cherubal, A. Chatterjee, and W. Kao, "Hierarchical specification-driven analog fault modeling for efficient fault simulation and diagnosis," in Proc. Int. Test Conf, 1997, pp. 903-912.
7. J.-L. Huang, C-Y Pan, and K. T. Cheng, "Specification back-propagation and its application to DC fault simulation for analog/mixed-signal circuits," in Proc. IEEE VLSI Test Symp., Apr. 1999, pp. 220-225.
8. N. Nagi and J. A. Abraham., "Hierarchical fault modeling for analog and mixed-signal circuits," in Proc. IEEE VLSI Test Symp., May 1992, pp. 96-101.
9. N. Nagi, A. Chatterjee, A. Balivada, and J. A. Abraham, "Fault-based automatic test generator for linear analog circuits," in Proc. IEEE Int. Conf. Comput.-Aided Des., Nov. 1993, pp. 88-9.1.
10. L. Milor and A. L. Sangiovanni-Vincentelli, "Minimizing production test time to detect faults in analog circuits," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 13, no. 6, pp. 796-813, Jun. 1994.
11. C Y. Chao, H. J. Lin, and L. Milor, "Optimal testing of VLSI analog circuits," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 16, no. l,pp. 58-77, Jan. 1997.
12. J. Starzyk and H. Dai, "Multifrequency measurement of testability in analog circuits," in Proc. Int. Symp. Circuits Syst., 1987, pp. 5884-5887.
13. M. Tian and R.-J. Shi, "Worst case tolerance analysis of linear analog circuits using sensitivity bands," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl, vol. 57, no. 8, pp. 1138-1145, Aug. 2000.
14. T. Koskinen and P. Y. K. Cheung, "Hierarchical tolerance analysis using statistical behavioral models," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 15, no. 5, pp. 506-516, May 1996.
15. N. B. Hamida and B. Kaminska, "Analog circuit testing based on sensitivity computation and new circuit modeling," in Proc. IEEE Int. Test Conf, Oct. 1993, pp. 652-661.
16. M. Slamani and B. Kaminska, "Analog circuit fault diagnosis based on sensitivity computation and functional testing," IEEE Des. Test Comput., vol. 9, no. 1, pp. 30-39, Mar. 1992.
17. F. Liu, J. J. Flomenberg, D. V. Yasaratne, and S. Ozev, "Hierarchical variance analysis for analog circuits based on graph modelling and correlation loop tracing," in Proc. IEEE Des. Autom. Test Eur. Conf, Mar. 2005, pp. 126-131.
18. S.Huynh, S. Kim, and M. Soma, "Automatic analog test signal generation using multifrequency analysis," IEEE Trans. Circuits Syst. II, Analog Digit. Signal. Process., vol. 46, no. 5, pp. 565-575, May 1999.
19. M. Soma, S. Huynh, J. Zhang, S. Kim, and G. Devarayanadurg, "Hierarchical ATPG for analog circuits and systems," IEEE Des. Test Comput., vol. 18, no. 1, pp. 72-8.1, Jan./Feb. 2001.
20. M. Slamani and B. Kaminska, "Testing analog circuits by sensitivity computation," in Proc. IEEE Eur. Conf. Des. Autom., Mar. 1992, pp. 532-537.
21. E. Acar and S. Ozev, "Defect-based RF testing using a new catastrophic fault model," in Proc. IEEE Int. Test Conf, Nov. 2005, pp. 421-429.
22. D. Gaitonde and D. M. H. Walker, "A circuit level fault model for resistive shorts of MOS gate oxide," in Proc. Int. Workshop Defect Fault Toler. VLSI Syst., Nov. 1991, pp. 63-66.
23. M. Bilodeau and D. Brenner, Theory of Multivariate Statistics. New York: Springer-Verlag, 1999.
24. A. Genz, "Numerical computation of multivariate normal probabilities," J. Comput. Graph. Stat., vol. 1, no. 2, pp. 141-149, Jun. 1992.
25. C. Clark, "The greatest of a finite set of random variables," Oper. Res., vol. 9, no. 2, pp. 145-162, Mar. 196.1.
26. J. A. Starzyk, D. Liu, Z.-H. Liu, D. E. Nelson, and J. O. Rutkowski, "Entropy-based optimum, test points selection for analog fault dictionary techniques," IEEE Trans. Instrum. Meas., vol. 53, no. 3, pp. 754-761, Jun. 2004.
27. L. Milor and V. Visvanathan, "Detection of catastrophic faults in analog integrated circuits," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 8, no. 2, pp. 114-130, Feb. 1989.
28. V. Stopjakova, P. Malosek, M. Matej, V. Nagy, and M. Margala, "Defect detection in analog and mixed circuits by neural networks using wavelet analysis," IEEE Trans. Rel, vol. 54, no. 3, pp. 441-448, Sep. 2005.
29. F. Azais, Y. Bertrand, M. .Renovell, A. Ivanov, and S. Tabatabaei, "An alldigital DFT scheme for testing catastrophic faults in PLLS," IEEE Des. Test Comput., vol. 20, no. 1, pp. 60-67, Jan./Feb. 2003.
30. M. Pronath, V. Gloeckel, and H. Graeb, "A parametric test method for analog components in integrated mixed-signal circuits," in Proc. IEEE Int. Conf. Comput.-Aided Des., Nov. 2000, pp. 557-561.
31. A. Petraglia, J. M. Canive, and M. R. Petraglia, "Efficient parametric fault detection in switched-capacitor filters," IEEE Des. Test Comput., vol. 23, no. 1, pp. 58-66, Jan./Feb. 2006.
32. H. H. Zhang, A. Balivada, and J. A. Abraham, "A novel test generation approach for parametric faults in linear analog circuits," in Proc. IEEE VLSI Test Symp., Apr. 1996, pp. 470-475.
33. T. Balen, A. Andrade, Jr., F. Azais, M. Lubaszewski, andM. Renovell, "An approach to the built-in self-test of field programmable analog arrays," in Proc. IEEE VLSI Test Symp., Apr. 2004, pp. 383-388.
34. C Y. Pan and K. T. Cheng, "Pseudo-random testing and signature analysis for mixed-signal circuits," in Proc. IEEE Int. Conf. Comput.-Aided Des., Nov. 1995, pp. 102-107.
35. J. Roh and J. A. Abraham, "A comprehensive signature analysis scheme for oscillation-test," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 22, no. 10, pp. 1409-1423, Oct. 2003.
36. Y Xing, "Defect-oriented testing of mixed-signal ICs: Some industrial experience," in Proc. IEEE Int. Test Conf, Nov. 1998, pp. 678-687.