BIST for measuring clock jitter of charge-pump phase-locked loops

IEEE Transactions on Instrumentation and Measurement

Volumn 57, Issue 2, 2008, Pages 276-285

  Hsu, Jen Chien ^a   Su, Chauchin ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

Analog built in self test (BIST); Jitter measurement; On chip measurement; Phase locked loop (PLL) BIST; Timeto digital converter (TDC)

Indexed keywords

MEASUREMENT ERRORS; OSCILLATORS (ELECTRONIC); PHASE LOCKED LOOPS; TIMING JITTER;

ANALOG BUILT-IN SELF-TEST; JITTER MEASUREMENT; ON-CHIP MEASUREMENT; TIME-TO-DIGITAL CONVERTER;

BUILT-IN SELF TEST;

EID: 39449134226     PISSN: 00189456     EISSN: None     Source Type: Journal    
DOI: 10.1109/TIM.2007.910109     Document Type: Article

References (15)

1. S. Sunter and A. Roy, "BIST for phase-locked loops in digital application," in Proc. ITC, 1999, pp. 532-540.
2. N. Abaskharoun and G. W. Roberts, "Circuits for on-chip sub-nanosecond signal capture and characterization," in Proc. IEEE Custom Integr. Circuits Conf., 2001, pp. 251-254.
3. A. H. Chan and G. W. Roberts, "A deep sub-micron tinting measurement circuit using a single-stage Vernier delay line," in Proc. IEEE Custom Integr. Circuits Conf., 2002, pp. 77-80.
4. T. Xia, H. Zheng, J. Li, and A. Ginawi, "Self-refereed on-chip jitter measurement circuit using Vernier oscillators," in Proc. IEEE Comput. Soc. Annu. Symp. VLSI, 2005, pp. 218-223.
5. K.-H. Chen, S.-Y. Jiang, and Z.-S. Chen, "BIST for clock jitter measurements," in Proc. Int. Symp. Circuits Syst., 2003, pp. 577-580.
6. C.-C. Tsai and C.-L. Lee, "An on-chip jitter measurement circuit for the PLL," in Proc. Asian Test Symp., 2003, pp. 332-335.
7. J.-J. Huang and J.-L. Huang, "A low-cost jitter measurement technique for BIST applications," in Proc. Asian Test Symp., 2003, pp. 336-339.
8. B. Nelson and M. Soma, "On-chip calibration technique for delay line based BIST jitter measurement," in Proc. Int. Symp. Circuits Syst. 2004, pp. 944-947.
9. S. Cherubal and A. Chatterjee, "A high-resolution jitter measurement technique using ADC sampling," in Proc. Int. Test Conf., 2001, pp. 838-847.
10. K. Taylor, B. Nelson, A. Chong, H. Nguyen, H. Lin, M. Soma, H. Haggag, J. Huard, and J. Braag, "Experimental results for high-speed jitter measurement technique," in Proc. Int. Test Conf., 2004, pp. 85-94.
11. K.-H. Cheng and S.-Y. Jiang, "High accuracy jitter measurement using cyclic pulse width modulation structure," in Proc. VLSI Des., Autom. Test, 2005, pp. 24-27.
12. M. Ishida, K. Ichiyama, T. J. Yamaguchi, M. Soma, M. Suda, T. Okayasu, D. Watanabe, and K. Yamamoto, "A programmable on-chip picosecond jitter-measurement circuit without a reference-clock input," in Proc. IEEE Int. Solid-State Circuits Conf., 2005, pp. 512-614.
13. T. Xia and J.-C. Lo, "Time-to-voltage converter for on-chip jitter measurement," IEEE Trans. Instrum. Meas., vol. 52, no. 6, pp. 1738-1748, Dec. 2003.
14. K. A. Jenkins, A. P. Jose, and D. F. Heidel, "An on-chip jitter measurement circuit with sub-picosecond resolution," in Proc. Eur. Solid-State Circuits Conf., 2005, pp. 157-160.
15. M. Chou, J. Hsu, and C. Su, "A digital BIST methodology for spread spectrum clock generators," in Proc. Asian Test Symp., 2006, pp. 251-254.