Dependable integration of full-porous low-k interconnect and low-leakage/ low-cost transistor for 45nm LSTP platform

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2007, Pages 174-175

  Sukegawa, K ^a   Yamamoto, T ^a   Kudo, H ^a   Kubo, T ^a   Sukegawa, T ^a   Ehara, H ^a   Ochmizu, H ^a   Fukuda, M ^a   Mizushima, Y ^a   Shimoda, Y ^a   Tajima, M ^a   Oryoji, M ^a   Nakata, Y ^a   Watatani, H ^a   Sakai, H ^a   Asneil, A ^a   Sakai, S ^a   Matauyama, H ^a   Kurata, H ^a   Taukune, A ^a   Shimizu, N ^a   Futatsugi, T ^a   Satoh, S ^a   Kase, M ^a   Sugii, T ^a   more..

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; COPPER; OPTICAL INTERCONNECTS; STRESSES;

ANNEALING PROCESSING; DAMASCENE CU INTERCONNECTS; MECHANICAL TOUGHNESS; POROUS LOW-K; RC DELAYS; STRESS MIGRATION (SM); VLSI TECHNOLOGIES; WIRE BONDING (WB);

NANOSTRUCTURED MATERIALS;

EID: 47249142371     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2007.4339681     Document Type: Conference Paper

References (7)

1. E.Josse et al., IEDM Tech Dig., p.693, 2006
2. Y.Yuan et al, Symp. VLSI Tech. p.124. 2006
3. A.Steegen et al., IEDM Tech Sig., p.69, 2005
4. S.C.Song et al., Symp. VLSI Tech., p.16, 2005
5. T.Hoffmann et al., Symp. VLSI Tech., p. 194, 2006
6. M.Saitoh et al., Symp. VLSI Tech., p.162, 2006
7. H. Sakai et al. MRS Adv. Metallization Conf., p.33, 2006.