A cost-effective LOP/LSTP integrated CMOS platform utilizing multi-thickness SiON gate dielectrics with hafnium for 45-nm node

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2007, Pages 176-177

  Tsutsui, Gen ^a   Maruyama, Shinya ^a   Abe, Tomohisa ^a   Nakamura, Hidetatsu ^a   Fukase, Tadashi ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COST EFFECTIVENESS; DIELECTRIC MATERIALS; FUZZY LOGIC; GATE DIELECTRICS; GATES (TRANSISTOR); HAFNIUM; ION BOMBARDMENT; ION IMPLANTATION; LOGIC CIRCUITS; MOLECULAR BEAM EPITAXY; NANOTECHNOLOGY; SURFACE ROUGHNESS; SWITCHING CIRCUITS; SWITCHING THEORY; TRANSISTORS;

45NM NODE; GATE STACKS; INTEGRATION TECHNIQUES; LOCAL STRESSES; LOW COST INTEGRATION; NARROW CHANNELS; SION GATE DIELECTRICS; TRANSISTOR PERFORMANCE; VLSI TECHNOLOGIES;

COST REDUCTION;

EID: 47249090437     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2007.4339682     Document Type: Conference Paper

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