0.525μm2 6T-SRAM bit cell using 45nm fully-depleted SOI CMOS technology with metal gate, high K dielectric and elevated source/drain on 300mm wafers

Proceedings - IEEE International SOI Conference

Volumn 2005, Issue , 2005, Pages 221-222

  Vandooren, A ^a   Hobbs, C ^a   Faynot, O ^d   Perreau, P ^d   Denorme, S ^c   Fenouillet Beranger, C ^d   Gallon, C ^c   Morin, C ^d   Zauner, A ^b   Imbert, G ^c   Bernard, H ^c   Garnier, P ^b   Gabette, L ^b   Broekaart, M ^b   Aminpur, M ^a   Barnola, S ^d   Loubet, N ^c   Dutartre, D ^c   Korman, T ^b   Chabanne, G ^a   Martin, F ^d   Le Tiec, Y ^d   Gierczynski, N ^b   Smith, S ^b   Laviron, C ^d   Bidaud, M ^b   Pouilloux, I ^b   Bensahel, D ^c   Skotnicki, T ^c   Mingam, H ^c   Wild, A ^a   more..

^a Freescale Semiconductors   (France)

^b PHILIPS RESEARCH LABORATORIES   (Germany)

^c STMICROELECTRONICS   (France)

^d CEA LETI   (France)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 33744759815     PISSN: 1078621X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOI.2005.1563595     Document Type: Conference Paper

References (5)

1. R. Chau et al., IEDM 2001, p. 621
2. B. Doris et al. IEDM 2002 p. 267
3. Z. Krivokapic et al., 2003 Symp. VLSI p. 131.
4. S. Samavedam et al., 2002 Symp. VLSI Tech. Dig., p.24
5. C.G. Sodini et al., Solid-State Electronics, vol. 25, pp. 833-841, 1982.