Effect of parasitic resistance and capacitance on performance of InGaAs HEMT digital logic circuits

IEEE Transactions on Electron Devices

Volumn 56, Issue 5, 2009, Pages 1161-1164

  Oh, Saeroonteer ^a   Wong, H S Philip ^a  

^a Stanford University   (United States)

Author keywords

Circuit delay; Device pitch scaling; Digital logic circuit; High electron mobility transistor (HEMT); III V; InGaAs InAlAs; Parasitic capacitance; Series resistance

Indexed keywords

CIRCUIT DELAY; DEVICE-PITCH SCALING; DIGITAL LOGIC CIRCUIT; HIGH-ELECTRON MOBILITY TRANSISTOR (HEMT); III-V; INGAAS/INALAS; PARASITIC CAPACITANCE; SERIES RESISTANCE;

CAPACITANCE; DIGITAL CIRCUITS; ELECTRIC NETWORK ANALYSIS; ELECTRON MOBILITY; FIELD EFFECT TRANSISTORS; HIGH ELECTRON MOBILITY TRANSISTORS; IMPACT RESISTANCE; LOGIC DEVICES; SEMICONDUCTING INDIUM; SEMICONDUCTOR DEVICES; SWITCHING CIRCUITS;

LOGIC CIRCUITS;

EID: 67349139272     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2009.2016027     Document Type: Article

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