Extending technology roadmap by selective device footprint scaling and parasitics engineering

International Symposium on VLSI Technology, Systems, and Applications, Proceedings

Volumn , Issue , 2008, Pages 159-160

  Deng, Jie ^a   Wei, Lan ^a   Chang, Li Wen ^a   Kim, Keunwoo ^b   Chuang, Ching Te ^b   Wong, H S Philip ^a  

^a Stanford University   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DEVICE STRUCTURES; INTERNATIONAL SYMPOSIUM; PARASITIC CAPACITANCES; PARASITIC RESISTANCES; PARASITICS; TECHNOLOGY ROADMAP; TECHNOLOGY SCALING; VLSI TECHNOLOGIES;

CAPACITANCE; CODES (SYMBOLS); IMPACT RESISTANCE; INDUSTRIAL MANAGEMENT; SECURITY SYSTEMS;

TECHNOLOGY;

EID: 49049119989     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTSA.2008.4530846     Document Type: Conference Paper

References (9)

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