50-nm self-aligned and "standard" T-gate InP pHEMT comparison: The influence of parasitics on performance at the 50-nm node

IEEE Transactions on Electron Devices

Volumn 53, Issue 12, 2006, Pages 2920-2925

  Moran, David A J ^a   McLelland, Helen ^a   Elgaid, Khaled ^a   Whyte, Griogair ^a   Stanley, Colin R ^a   Thayne, Iain ^a  

^a UNIVERSITY OF GLASGOW   (United Kingdom)

Author keywords

Access resistance; Fringing capacitance; InP; MODFETs; Nonalloyed; Parasitics; Self aligned gate

Indexed keywords

CAPACITANCE; GATES (TRANSISTOR); MOSFET DEVICES; OPTIMIZATION; SEMICONDUCTING INDIUM PHOSPHIDE;

ACCESS RESISTANCE; GATE FRINGING CAPACITANCES; PARASITIC CAPACITANCES; SELF ALIGNED GATE;

HIGH ELECTRON MOBILITY TRANSISTORS;

EID: 33947211936     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2006.885674     Document Type: Article

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