Beyond CMOS: Logic suitability of In0.7Ga0.3As HEMT

2006 International Conference on Compound Semiconductor Manufacturing Technology

Volumn , Issue , 2006, Pages 251-254

  Kim, Dae Hyun ^a   Delalamo, Jesús A ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

DIBL; Gate delay (CV I); HEMT; ION IOFF; Logic; Subthreshold slope (s)

Indexed keywords

DIBL; DRAIN-INDUCED BARRIER LOWERING; ELECTROSTATIC INTEGRITY; GATE DELAYS; LOGIC; LOGIC CHARACTERISTICS; PARASITIC RESISTANCES; SUBTHRESHOLD SLOPE;

SEMICONDUCTOR DEVICE MANUFACTURE;

HIGH ELECTRON MOBILITY TRANSISTORS;

EID: 84887476012     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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