Diagnosis of design-silicon timing mismatch with feature encoding and importance ranking - The methodology explained

Proceedings - International Test Conference

Volumn , Issue , 2008, Pages

  Bastani, Pouria ^a   Callegari, Nick ^a   Wang, Li C ^a   Abadir, Magdy S ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b 2Freescale Semiconductor Inc

Author keywords

[No Author keywords available]

Indexed keywords

ASIC DESIGN; KERNEL FUNCTION; PATH-BASED; TIMING MISMATCH;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; EDUCATION; INTEGRATED CIRCUITS; LEARNING ALGORITHMS; TIME MEASUREMENT;

DESIGN;

EID: 67249137738     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.2008.4700588     Document Type: Conference Paper

References (38)

1. K. Killpack, et al," "Analysis of Causation of Speed Failures in a Microprocessor: A Case Study," To appear in IEEE Design & Test Special Issue on Silicon Debug and Diagnosis 2008.
2. C. Bittlestone, A. Hill, V. Singhal, Arvind N.V, "Architecting ASIC Libraries and Flows in the Nanometer Era," In DAC 2003.
3. Li-C. Wang, Pouria Bastani, Magdy S. Abadir, "Design-silicon timing correlation - a data mining perspective," In DAC 2007.
4. P. Bastani, B. Lee, L.Wang, S. Sundareswaran, M. Abadir, "Analyzing the risk of timing modeling based on path delay tests," ITC2007.
5. P. Bastani, et al, "An Improved Feature Ranking Method for Diagnosis of Systematic Timing Uncertainty," VLSI-DAT 2008.
6. P. Bastani, N. Callegari, L. Wang, M. Abadir, "Statistical Diagnosis of Unmodeled Timing Effect," Submitted to DAC 2008.
7. M. Abramovici, M. Breuer. "Fault Diagnosis Based on Effect-Cause Analysis: An Introduction," In DAC 1980, pp. 69-76.
8. Y.-C. Hsu and S.K. Gupta. "A New Path-Oriented Effect-Cause Methodology to Diagnose Delay Failures," ITC, 1998, pp. 758-767.
9. Z.Wang, et al, "An Efficient and Effective Methodology on the Multiple Fault Diagnosis," In ITC 2003, pp. 329-338.
10. A. Kristic, et al, "Delay Defect Diagnosis Based Upon Statistical Timing Models - The First Step," In DATE 2003.
11. P. Zuchowski, P. Habitz, J. Hayes, J. Oppold, "Process and Environmental Variation Impacts on ASIC Timing," In ICCAD 2004.
12. S. Nassif, "Design for Variability in DSM Technologies," In IEEE International Symposium on Quality Electronic Design 2000.
13. S. Nassif, "Modeling and Forecasting of Manufacturing Variations," In International Workshop on Statistical Metrology, 2000.
14. D. Josephson, et al, "Debug Methodology for the McKinley Processor," In ITC 2001. pp 451-460.
15. D. Josephson, "The Manic Depression of Microprocessor Debug," In ITC 2002.
16. W. Huott, et al, "The Attack of the 'Holey Shmoos': A Case Study of Advanced DFD and Picosecond Imaging Analysis,"In ITC 1999.
17. C. Pryon, et al, "Silicon Symptoms to Solutions: Applying Designfor- Debug Techniques," In ITC 2002.
18. M. Bass, et al, "Design Methodologies for the PA 71000LC Microprocessor," In Hewlett-Packard Journal, 46(2):23-25 April 1995.
19. D. Josephson, "The Good, the Bad, and the Ugly of Silicon Debug," In DAC 2006.
20. T. Thiel, "Have I Really Met Timing? - Validating PrimeTime Timing Reports with Spice," In DATE 2004.
21. O. Sinanoglu, P. Schremmer, "Diagnosis, Modeling and Tolerance of Scan Chain Hold-Time Violations," In DATE 2007.
22. N. NS, T. Bonifield, et al, "BEOL Variability and Impact on RC Extraction," In DAC 2005.
23. U. Narasimha, A. Hill, N. NS, "SmartExtract: Accurate Capacitance Extraction for SOC Designs," In IEEE VLSI Design 2006.
24. P. Larsson and C. Svensson, "Noise in digital dynamic CMOS circuits," In IEEE J. Solid-State Circuits June 1994, pp. 655-663.
25. Sanjay Pant, Eli Chiprout, "Power Grid Physics and Implications for CAD," In Proc. DAC 2006.
26. P. Bastani, K. Killpack, L.Wang, E. Chiprout, "Speedpath prediction based on learning from small set of exmaples," Submitted to DAC'08.
27. V. Vapnik The Nature of Statistical Learning Theory. Springer 1999.
28. Nello Cristianini, John Shawe-Taylor. An Introduction to Support Vector Machine. Cambridge University Press, 2002
29. J. Shawe-Taylor, N. Cristianini, Kernel Methods for Pattern Analysis, Cambridge University Press 2004.
30. Leo Breiman, "Random Forests," In Machine Learning Journal 45 pp. 5-32, 2001.
31. S. Kulkarni, D. Sylvester, D. Blaauw, "A Statistical Framework for Post-Silicon Tuning through Body Bias Clustering," In ICCAD 2006.
32. M. Najibi, et al, "Dynamic Voltage and Frequency Management Based on Variable Update Intervals for Freq. Setting," ICCAD 2006.
33. B. Quinton, et al, "Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow," ICCAD 2005.
34. R. Livengood, "Design for Debug for Silicon Microsurgery and Probing of Flip-Chip Packaged Integrated Circuits," In ITC 1999.
35. Lakshmanan, et al, "Incremental Dummy Metal Insertion," US Patent No. 7,260,803 B2. August 2007
36. L. Tien, "Method for reducing layer revision in an engineering change order," US Patent No. 7,137,094. November 2006.
37. K. Chang, I. Markov, V. Bertacco, "Automating Post-Silicon Debugging and Repair," ICCAD 2007.
38. L. Yuan, S. Leventhal, G. Qu, "Temperature-Aware Leakage Minimization Technique for Real-Time Systesms," ICCAD 2006.