Delay defect diagnosis based upon statistical timing models - The first step

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2003, Pages 328-333

  Krstic, Angela ^a   Wang, Li C ^a   Cheng, Kwang Ting ^a   Liou, Jing Jia ^b   Abadir, Magdy S ^c  

^a University of California   (United States)

^b NATIONAL TSING HUA UNIVERSITY   (Taiwan)

^c MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARK CIRCUIT; DEFECT INJECTIONS; DELAY DEFECT DIAGNOSIS; DIAGNOSIS ALGORITHMS; DIAGNOSIS PROBLEM; STATISTICAL DELAYS; STATISTICAL TIMING; STATISTICAL TIMING ANALYSIS;

DEFECTS;

EXHIBITIONS;

EID: 84893805472     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2003.1253628     Document Type: Conference Paper

References (18)

1. K. Baker, G. Gronthoud, M. Lousberg, I. Schanstra, , and C. Hawkins. Defect-Based Delay Testing of Resistive Vias-Contacts, A Critical Evaluation. Proceedings of IEEE International Test Conference, pages 467-476, September 1999.
2. M. A. Breuer, C. Gleason, and S. Gupta. New Validation and Test Problems for High Performance Deep Sub-Micron VLSI Circuits. Tutorial Notes, IEEE VLSI Test Symposium, April 1997.
3. Robert C. Aitken, ?Nanometer Technology Effects on Fault Models for IC Testing?, IEEE Computer, November 1999, pp. 46-51
4. K-T Cheng, S. Dey, M. Rodgers, and K. Roy, Test Challenges for Deep Sub-Micron Technologies, ACM/IEEE Design Automation Conference 2000.
5. J-J. Liou, A. Krstíc, K-T. Cheng, D. Mukherjee, and S. Kundu. Performance Sensitivity Analysis Using Statistical Methods and Its Applications to Delay Testing. Proceedings of Asian South Pacific Design Automation Coneference, pages 587-592, January 2000.
6. Miron Abramovici, Melvin A. Breuer, and Arthur D. Friedman, Chapter 12: Logic Level Diagnosis, Digital Systems Testing and Testable Design, W.H.Freeman, 1990.
7. Irith Pomeranz, and Sudhakar M. Reddy, Location of Stuck-At Faults and Bridging Faults Based on Circuit Partitioning IEEE Trans. on Computers, 1998, pp. 1124-1135
8. D. B. Lavo, B. Chess, T. Larrabee, and F. J. Ferguson, Diagnosing Realistic Bridging Faults with Single Stuck-At Information. IEEE Transactions on Computer-Aided Design, pp. 255-268, March, 1998.
9. J. Ghosh-Dastidar, and N. A. Touba, Diagnosing Resistive Bridges Using Adaptive Techniques. IEEE Custom Integrated Circuits Conference, pp. 79-82, 2000.
10. M. Sivaraman, and A. J. Strojwas, Path Delay Fault Diagnosis and Coverage-A Metric and an Estimation Technique. IEEE Transactions on Computer-Aided Design, pp. 440-457, March, 2001.
11. A. Krstic, J-J. Liou, Y-M. Jiang, and K-T. Cheng, Delay Testing Considering Crosstalk-Induced Effects. IEEE International Test Conference, pp. 558-567, October, 2001.
12. W-Y. Chen, S. K. Gupta, and M. A. Breuer, Test Generation for Crosstalk-Induced Delay in Integrated Circuits. IEEE International Test Conference, pp. 191-200, October, 1999.
13. P. Girard, C. Landrault, and S. Pravosssudovitch, A Novel Approach to Delay-Fault Diagnosis. Design Automation Conference, pp. 357-360, June, 1992.
14. P. Pant, and A. Chatterjee, Path-Delay Fault Diagnosis in Non-Scan Sequential Circuits with At-Speed Test Application. IEEE International Test Conference, pp. 245-252, October, 2000.
15. Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu, A New Method for Diagnosing Multiple Stuck-At Faults using Multiple and Single Fault Simulations, Proceedings of 17th IEEE VLSI Test Symposium, 1999.
16. J-J. Liou, K-T. Cheng, and D. Mukherjee. Path Selection for Delay Testing of Deep Sub-Micron Devices Using Statistical Performance Sensitivity Analysis. Proceedings of IEEE VLSI Test Symposium, pages 97-104, April 2000.
17. J-J. Liou, A. Krstic, L-C. Wang, and K-T. Cheng. False-Path-Aware Statistical Timing Analysis and Efficient Path Selection for Delay Testing and Timing Validation. Proceedings of Design Automation Conference, June 2002.
18. Anacad. Eldo v4.4.x User?s Manual. 1996.