Communication latency aware low power NoC synthesis

Proceedings - Design Automation Conference

Volumn , Issue , 2006, Pages 574-579

  Hu, Yuanfang ^a   Zhu, Yi ^a   Chen, Hongyu ^b   Graham, Ronald ^a   Cheng, Chung Kuan ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b SYNOPSYS INC   (United States)

Author keywords

Latency; Network on chip; Power; Topology

Indexed keywords

ALGORITHMS; CIRCUIT SIMULATION; ELECTRIC POWER UTILIZATION; ENERGY EFFICIENCY; FREQUENCY ALLOCATION; POLYNOMIAL APPROXIMATION; TOPOLOGY;

COMMUNICATION BANDWIDTH; COMMUNICATION LATENCY; NETWORK-ON-CHIP;

MICROPROCESSOR CHIPS;

EID: 34547227349     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1146909.1147058     Document Type: Conference Paper

References (13)

1. H. Chen, R. Shi, C.K. Cheng, and D. Harris, "Surfliner: A Distortionless Electrical Signaling Scheme for Speed of Light On-Chip Communications," IEEE Intl. Conf. on Computer Design, pp.497-502, Oct. 2005.
2. W. J. Dally and B. Towles, "Route Packets, Not Wires: On-Chip Interconnection Networks," ACM/IEEE Design Automation Conf., pp. 684-689, June 2001.
3. N. Garg, and J. Konemann, "Faster and simpler algorithms for multicommodity flow and other fractional packing problems," the 39th Annual IEEE Symp. on Foundations of Computer Science, pp. 300-309, Nov. 1998.
4. J. Hu and R. Marculescu, "Energy-Aware Mapping for Tile-based NoC Architectures Under Performance Constraints," Asia and South Pacific Design Automation Conf., pp. 233-239, Jan. 2003.
5. Y. Hu, H. Chen, Y. Zhu, A. A. Chien, and CK. Cheng, "Physical Synthesis of Energy-Efficient Networks-on-Chip Through Topology Exploration and Wire Style Optimization," Intl. Conf. on Computer Design, pp. 111-118, Oct. 2005.
6. G. Karakostas, "Faster approximation schemes for fractional multicommodity flow problems", the 13th Annual ACM/SIAM Symp. on Discrete Algorithms, pp. 166-173, 2002.
7. U.Y. Ogras and R. Marculescu, "Application-Specific Network-on-Chip Architecture Customization Vis Long-Range Link Insertion", Intl. Conf. on Computer Aided Design, pp. 246-253, Nov., 2005.
8. L.S. Peh, "Flow Control and Micro-Architectural Mechanisms for Extending the Performance of Interconnection Networks", Ph.D. Thesis, Stanford University, August, 2001.
9. C. Seitz, "Let's Route Packets Instead of Wires", Advanced Research in VLSI: Proceedings of the Sixth MIT Conference, pp. 133-138, 1990.
10. H. Wang, L. S. Peh, and S. Malik, "Orion: A Power-Performance Simulator for Interconnection network," Intl. Symp. on Microarchitecture, pp. 294-305, Nov. 2002.
11. H. Wang, L. S. Peh, and S. Malik, "A Technology-aware and Energy-oriented Topology Exploration for On-chip Networks," Design, Automation and Test in Europe, pp.1238-1243, Vol.2, Mar. 2005.
12. T. T. Ye, L. Benini, and G. De Micheli, "Analysis of Power Consumption on Switch Fabrics in Network Routers," ACM/IEEE Design Automation Conf., pp.524-529, June, 2002.
13. http://public.itrs.net