Exact multiple-control toffoli network synthesis with SAT techniques

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 28, Issue 5, 2009, Pages 703-715

  Große, Daniel ^a   Wille, Robert ^a   Dueck, Gerhard W ^b   Drechsler, Rolf ^a  

^a UNIVERSITY OF BREMEN   (Germany)

^b UNIVERSITY OF NEW BRUNSWICK   (Canada)

Author keywords

Logic synthesis; Quantum computing; Reversible logic; Satisfiability (SAT); Toffoli gates

Indexed keywords

LOGIC SYNTHESIS; QUANTUM COMPUTING; REVERSIBLE LOGIC; SATISFIABILITY (SAT); TOFFOLI GATES;

BOOLEAN FUNCTIONS; DECISION THEORY; HEURISTIC METHODS; LOGIC GATES; OPTICAL DATA PROCESSING; QUANTUM COMPUTERS; QUANTUM THEORY;

ALGORITHMS;

EID: 65349142610     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2009.2017215     Document Type: Article

References (46)

1. D. Große, X. Chen, G. W. Dueck, and R. Drechsler, "Exact SAT-based Toffoli network synthesis," in ACM Great Lakes Symp. VLSI, 2007, pp. 96-101.
2. R. Wille and D. Große, "Fast exact Toffoli network synthesis of reversible logic," in Int. Conf. CAD, 2007, pp. 60-64.
3. R. Landauer, "Irreversibility and heat generation in the computing process," IBM J. Res. Develop., vol. 5, no. 3, p. 183, 1961.
4. M. Nielsen and I. Chuang, Quantum Computation and Quantum Information. Cambridge, U.K.: Cambridge Univ. Press, 2000.
5. C. H. Bennett, "Logical reversibility of computation," IBM J. Res. Develop., vol. 17, no. 6, pp. 525-532, 1973.
6. T. Toffoli, "Reversible computing," in Automata, Languages and Programming, W. de Bakker and J. van Leeuwen, Eds. Berlin, Germany: Springer-Verlag, 1980, p. 632. Technical Memo MIT/LCS/TM-151, MIT Lab. for Comput. Sci.
7. E. F. Fredkin and T. Toffoli, "Conservative logic," Int. J. Theor. Phys., vol. 21, no. 3/4, pp. 219-253, Apr. 1982.
8. A. Peres, "Reversible logic and quantum computers," Phys. Rev. A, Gen. Phys., vol. 32, no. 6, pp. 3266-3276, Dec. 1985.
9. A. Barenco, C. H. Bennett, R. Cleve, D. P. DiVinchenzo, N. Margolus, P. Shor, T. Sleator, J. A. Smolin, and H. Weinfurter, "Elementary gates for quantum computation," Phys. Rev. A, Gen. Phys., vol. 52, no. 5, pp. 34573467, Nov. 1995.
10. D. M. Miller and G. W. Dueck, "Spectral techniques for reversible logic synthesis," in 6th Int. Symp. Representations Methodology Future Comput. Technol., 2003, pp. 56-62.
11. P. Gupta, A. Agrawal, and N. Jha, "An algorithm for synthesis of reversible logic circuits," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 25, no. 11, pp. 2317-2330, Nov. 2006.
12. D. M. Miller, D. Maslov, and G. W. Dueck, "A transformation based algorithm for reversible logic synthesis," in Des. Autom. Conf., 2003, pp. 318-323.
13. D. Maslov, G. W. Dueck, and D. M. Miller, "Toffoli network, synthesis with templates," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 24, no. 6, pp. 807-817, Jun. 2005.
14. L. Storme, A. D. Vos, and G. Jacobs, "Group theoretical aspects of reversible logic gates," J. Univers. Comput. Sci., vol. 5, pp. 307-321, 1999.
15. M. Saeedi, M. Sedighi, and M. S. Zamani, "A novel synthesis algorithm for reversible circuits," in Int. Conf. CAD, 2007, pp. 65-68.
16. V. V. Shende, A. K. Prasad, I. L. Markov, and J. P. Hayes, "Reversible logic circuit synthesis," in Int. Conf. CAD, 2002, pp. 353-360.
17. V. V. Shende, A. K. Prasad, I. L. Markov, and J. P. Hayes, "Synthesis of reversible logic circuits," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 22, no. 6, pp. 710-722, Jun. 2003.
18. G. Yang, X. Song, W. N. N. Hung, and M. A. Perkowski, "Fast synthesis of exact minimal reversible circuits using group theory," in ASP Des. Autom. Conf., 2005, pp. 1002-1005.
19. W. Hung, X. Song, G. Yang, J. Yang, and M. Perkowski, "Optimal synthesis of multiple output Boolean functions using a set of quantum gates by symbolic reachability analysis," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 25, no. 9, pp. 1652-1663, Sep. 2006.
20. R. Wille, G. Fey, D. Große, S. Eggersglüß, and R. Drechsler, "Sword: A SAT like prover using word level information," in VLSI Syst.-on-Chip, 2007, pp. 88-93.
21. D. Maslov and G. W. Dueck, "Reversible cascades with minimal garbage," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 23, no. 11, pp. 1497-1509, Nov. 2004.
22. R. Wille, D. Große, L. Teuber, G. W. Dueck, and R. Drechsler, "RevLib: An online resource for reversible functions and reversible circuits," in Int. Symp. Multi-Valued Logic, 2008, pp. 220-225. [Online]. Available: http://www.revlib.org
23. D. Maslov and D. M. Miller, "Comparison of the cost metrics through investigation of the relation between optimal NCV and optimal NCT 3-qubit reversible circuits," IET Comput. Digit. Tech., vol. 1, no. 2, pp. 98-104, 2007.
24. D. Maslov and G. W. Dueck, "Improved quantum cost for n-bit Toffoli gates," Electron. Lett., vol. 39, no. 25, pp. 1790-1791, Dec. 2004.
25. D. Maslov, C. Young, G. W Dueck, and D. M. Miller, "Quantum circuit simplification using templates," in Des. Autom. Test Eur., 2005, pp. 1208-1213.
26. S. Cook, "The complexity of theorem proving procedures," in ACM Symp. Theory Comput., 1971, pp. 151-158.
27. T. Larrabee, 'Test pattern generation using Boolean satisfiability," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 11, no. 1, pp. 415, Jan. 1992.
28. J. Shi, G. Fey, R. Drechsler, A. Glowatz, F. Hapke, and J. Schlöffel, "PASSAT: Efficient SAT-based test pattern generation for industrial circuits," in IEEE Annu. Symp. VLSI, 2005, pp. 212-217.
29. J. Zhang, S. Sinha, A. Mishchenko, R. Brayton, and M. ChrzanowskaJeske, "Simulation and satisfiability in logic synthesis," in Int. Workshop Logic Synth., 2005, pp. 161-168.
30. A. Smith, A. G. Veneris, M. F. Ali, and A. Viglas, "Fault diagnosis and logic debugging using Boolean satisfiability," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 24, no. 10, pp. 1606-1621, Oct. 2005.
31. A. Biere, A. Cimatti, E. Clarke, and Y. Zhu, "Symbolic model checking without BDDs," in Tools and Algorithms for the Construction and Analysis of Systems, vol. 1579. Berlin, Germany: Springer-Verlag, 1999, pp. 193-207.
32. E. M. Clarke, A. Biere, R. Raimi, and Y. Zhu, "Bounded model checking using satisfiability solving," Form. Methods Syst. Des., vol. 19, no. 1, pp. 7-34, Jul. 2001.
33. M. R. Prasad, A. Biere, and A. Gupta, "A survey of recent advances in SAT-based formal verification," Int. J. Softw. Tools Technol. Transf., vol. 7, no. 2, pp. 156-173, 2005.
34. M. Davis and H. Putnam, "A computing procedure for quantification theory," J. ACM, vol. 7, no. 3, pp. 506-521, Jul. 1960.
35. M. Davis, G. Logeman, and D. Loveland, "A machine program for theorem-proving," Commun. ACM, vol. 5, no. 7, pp. 394-397, Jul. 1962.
36. J. Marques-Silva and K. Sakallah, "A search algorithm, for propositional satisfiability," IEEE Trans. Comput., vol. 48, no. 5, pp. 506-521, May 1999.
37. M. Moskewicz, C. Madigan, Y. Zhao, L. Zhang, and S. Malik, "Chaff: Engineering an efficient SAT solver," in Des. Autom. Conf., 2001, pp. 530-535.
38. N. Een and N. Sörensson, "An extensible SAT-solver," in SAT, vol. 2919. Berlin, Germany: Springer-Verlag, 2004, pp. 502-518.
39. E. Goldberg and Y. Novikov, "BerkMin: A fast and robust SAT-solver," in Des. Autom. Test Eur., 2002, pp. 142-149.
40. M. Bozzano, R. Bruttomesso, A. Cimatti, T. Junttila, P. Rossum, S. Schulz, and R. Sebastiani, 'The MathSAT 3 system," in Int. Conf. Autom. Deduction, 2005, pp. 315-321.
41. B. Dutertre and L. Moura, The YICES SMT Solver; 2006. [Online]. Available: http://yices.csl.sri.com/
42. G. Tseitin, "On the complexity of derivation in propositional calculus," in Studies in Constructive Mathematics and Mathematical Logic. New York: Consultants Bureau, pt. 2, 1968, pp. 115-125.
43. G. Tseitin, "On the complexity of derivation in propositional calculus," in Automation of Reasoning, vol. 2, J. Siekmann and G. Wrightson, Eds. Berlin, Germany: Springer-Verlag, 1983, pp. 466-483.
44. C. Barrett, D. Dill, and J. Levitt, "A decision procedure for bit-vector arithmetic," in Des. Autom. Conf., 1998, pp. 522-527.
45. J. Marques-Silva, "The impact of branching heuristics in propositional satisfiability algorithms," in 9th Portuguese Conf. Artif. Intell. EPIA, 1999.
46. D. Maslov, G. W. Dueck, and N. Scott, Reversible Logic Synthesis Benchmarks Page. [Online]. Available: http://www.cs.uvic.ca/~dmaslov/