Exact sat-based toffoli network synthesis

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn , Issue , 2007, Pages 96-101

  Groe, Daniel ^a   Chen, Xiaobo ^a   Dueck, Gerhard W ^b   Drechsler, Rolf ^a  

^a UNIVERSITY OF BREMEN   (Germany)

^b UNIVERSITY OF NEW BRUNSWICK   (Canada)

Author keywords

Boolean satisfiability; Minimization; Quantum circuits; Reversible logic; Synthesis

Indexed keywords

ALGORITHMS; FUNCTION EVALUATION; ITERATIVE METHODS; LOGIC GATES; PROBLEM SOLVING; SET THEORY;

BOOLEAN SATISFIABILITY; QUANTUM CIRCUITS; REVERSIBLE LOGIC;

QUANTUM COMPUTERS;

EID: 34748897094     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1228784.1228812     Document Type: Conference Paper

References (14)

1. S. Cook. The complexity of theorem proving procedures. In S. ACM Symposium on Theory of Computing, pages 151-158, 1971.
2. N. Eén and N. Sörensson. An extensible SAT solver. In SAT 2003, volume 2919 of LNCS, pages 502-518, 2004.
3. D. Große, X. Chen, and R. Drechsler. Exact toffoli network synthesis of reversible logic using boolean satisfiability. In IEEE Dallas/CAS Workshop, pages 51-54, 2006.
4. P. Gupta, A. Agrawal, and N. Jha. An algorithm for synthesis of reversible logic circuits. IEEE Trans. on CAD of Integrated Circuits and Systems, 25(11):2317-2330, 2006.
5. W. Hung, X. Song, G. Yang, J. Yang, and M. Perkowski. Optimal synthesis of multiple output Boolean functions using a set of quantum gates by symbolic reachability analysis. IEEE Trans. on CAD of Integrated Circuits and Systems, 25(9):1652-1663, 2006.
6. T. Larrabee. Test pattern generation using Boolean satisfiability. IEEE Trans. on CAD, 11:4-15, 1992.
7. D. Maslov. Reversible Logic Synthesis Benchmarks Page. http://www.cs.uvic.ca/~dmaslov/.
8. D. Maslov and G. W. Dueck. Reversible cascades with minimal garbage. IEEE Trans. on CAD of Integrated Circuits and Systems, 23(11):1497-1509, 2003.
9. D. Maslov, G. W. Dueck, and D. M. Miller. Toffoli network synthesis with templates. IEEE Trans. on CAD of Integrated Circuits and Systems, 24(6):807-817, 2005.
10. D. M. Miller and G. W. Dueck. Spectral techniques for reversible logic synthesis. In 6th International Symposium on Representations and Methodology of Future Computing Technology, pages 56-62, 2003.
11. D. M. Miller, D. Maslov, and G. W. Dueck. A transformation based algorithm for reversible logic synthesis. In Design Automation Conf., pages 318-323, 2003.
12. M. A. Nielsen and I. Chuang. Quantum computation and quantum information. Cambridge University Press, 2000.
13. V. Shende, A. Prasad, I. Markov, and J. Hayes. Reversible logic circuit synthesis. In Int'l Conf. on CAD, pages pp. 353-360, 2002.
14. T. Toffoli. Reversible computing. In W. de Bakker and J. van Leeuwen, editors, Automata, Languages and Programming, page 632. Springer, 1980. Technical Memo MIT/LCS/TM-151, MIT Lab. for Comput. Sci.