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Volumn , Issue , 2009, Pages 690-695

Design methods for pipeline & delta-sigma A-to-D converters with convex optimization

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG DESIGNS; ANALOG-TO-DIGITAL CONVERTERS; CIRCUIT PERFORMANCE; DELTA SIGMAS; DELTA-SIGMA MODULATORS; DESIGN METHODS; DESIGN VARIABLES; LAYOUT CONSTRAINTS; LOW-POWER; OPTIMAL SOLUTIONS; OPTIMIZATION ENVIRONMENTS; OPTIMIZATION PROCEDURES; OPTIMIZER; PIPELINED ADCS; POWER EFFICIENCIES; SMALL AREAS; SYSTEM LSIS;

EID: 64549130804     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2009.4796560     Document Type: Conference Paper
Times cited : (10)

References (27)
  • 1
    • 64549085783 scopus 로고    scopus 로고
    • Maria del Mar Hershenson, Design of Pipeline Analog-to-Digital Converters via Geometric Programming, American Control Conference, 2004. Proceedings of the 2004, 4, pp. 3266-3271, Jun. 2004.
    • Maria del Mar Hershenson, "Design of Pipeline Analog-to-Digital Converters via Geometric Programming," American Control Conference, 2004. Proceedings of the 2004, vol. 4, pp. 3266-3271, Jun. 2004.
  • 2
    • 22544465883 scopus 로고    scopus 로고
    • T. N. Andersen, B. Hernes, A. Briskemyr, F. Telst0, J. Bj0rnsen, T. E. Bonnerud, and Ø. Moldsvor, A Cost-Efficient High-Speed 12-bit Pipeline ADC in Ø.18-μm Digital CMOS, IEEE J.Solid-State Circuits, 40, no. 7, pp.1506-1513, Jul. 2005.
    • T. N. Andersen, B. Hernes, A. Briskemyr, F. Telst0, J. Bj0rnsen, T. E. Bonnerud, and Ø. Moldsvor, "A Cost-Efficient High-Speed 12-bit Pipeline ADC in Ø.18-μm Digital CMOS," IEEE J.Solid-State Circuits, vol. 40, no. 7, pp.1506-1513, Jul. 2005.
  • 3
    • 33750836390 scopus 로고    scopus 로고
    • A 14-bit 20-MS/s Pipelined ADC With Digital Distortion Calibration
    • Nov
    • M. Daito, H. Matsui, M. Ueda, and K. Iizuka, "A 14-bit 20-MS/s Pipelined ADC With Digital Distortion Calibration," IEEE J. Solid-State Circuits, vol. 41, no. 11, pp.2417-2423, Nov. 2006.
    • (2006) IEEE J. Solid-State Circuits , vol.41 , Issue.11 , pp. 2417-2423
    • Daito, M.1    Matsui, H.2    Ueda, M.3    Iizuka, K.4
  • 4
    • 64549133620 scopus 로고    scopus 로고
    • J. P. Keane, P. J. Hurst, and S. H. Lewis, Digital Background
    • J. P. Keane, P. J. Hurst, and S. H. Lewis, "Digital Background
  • 5
    • 33645834775 scopus 로고    scopus 로고
    • Calibration for Memory Effects in Pipelined Analog-to-Digital Converters, IEEE J. Solid-State Circuits, 53, no. 3, pp.511-525, Mar. 2006.
    • Calibration for Memory Effects in Pipelined Analog-to-Digital Converters," IEEE J. Solid-State Circuits, vol. 53, no. 3, pp.511-525, Mar. 2006.
  • 6
    • 64549089459 scopus 로고    scopus 로고
    • The Effects of Switch Resistances on Pipelined ADC Performances and the Optimization for the Settling Time
    • Jun
    • M. Miyahara, and A. Matsuzawa, "The Effects of Switch Resistances on Pipelined ADC Performances and the Optimization for the Settling Time, " IEICE Trans. Electron, vol. E90-C, no. 6, pp. 1165-1171, Jun. 2007.
    • (2007) IEICE Trans. Electron , vol.E90-C , Issue.6 , pp. 1165-1171
    • Miyahara, M.1    Matsuzawa, A.2
  • 8
    • 84865443850 scopus 로고    scopus 로고
    • 55-mW 1.2-V 12-bit 100-MSPS Pipeline ADCs for Wireless Receivers
    • Sep
    • T. Ito, D. Kurose, T. Ueno, T. Yamaji, and T. Itakura, "55-mW 1.2-V 12-bit 100-MSPS Pipeline ADCs for Wireless Receivers," Proceedings of ESSCIRC 2006, pp. 540-543, Sep. 2006.
    • (2006) Proceedings of ESSCIRC , pp. 540-543
    • Ito, T.1    Kurose, D.2    Ueno, T.3    Yamaji, T.4    Itakura, T.5
  • 9
    • 33745172171 scopus 로고    scopus 로고
    • A 14bit Digitally Self-Calibrated Pipelined ADC with Adaptive Bias Optimization for Arbitrary Speeds up to 40MS/s
    • Jun
    • H. Matsui, M. Ueda, M. Daito, and K. Iizuka, "A 14bit Digitally Self-Calibrated Pipelined ADC with Adaptive Bias Optimization for Arbitrary Speeds up to 40MS/s," in Symp. VLSI Circuits Dig. Tech. Papers, 2005, pp. 330-333, Jun 2005.
    • (2005) Symp. VLSI Circuits Dig. Tech. Papers , vol.2005 , pp. 330-333
    • Matsui, H.1    Ueda, M.2    Daito, M.3    Iizuka, K.4
  • 11
    • 18444378113 scopus 로고    scopus 로고
    • A 12-bit 80-MSample/s Pipelined ADC With Bootstrapped Digital Calibration
    • May
    • C. R. Grace, P. J. Hurst, and S. H. Lewis, "A 12-bit 80-MSample/s Pipelined ADC With Bootstrapped Digital Calibration," IEEE J. Solid-State Circuits, vol. 40, no. 5, pp. 1038-1046, May 2005.
    • (2005) IEEE J. Solid-State Circuits , vol.40 , Issue.5 , pp. 1038-1046
    • Grace, C.R.1    Hurst, P.J.2    Lewis, S.H.3
  • 13
    • 10444266682 scopus 로고    scopus 로고
    • A 14-b 12-MS/s CMOS Pipeline ADC With Over 100-dB SFDR
    • Dec
    • Y. Chiu, P. R. Gray, and B. Nikolic, "A 14-b 12-MS/s CMOS Pipeline ADC With Over 100-dB SFDR,"IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2139- 2151, Dec. 2004.
    • (2004) IEEE J. Solid-State Circuits , vol.39 , Issue.12 , pp. 2139-2151
    • Chiu, Y.1    Gray, P.R.2    Nikolic, B.3
  • 14
    • 18444384772 scopus 로고    scopus 로고
    • A 15-b 40-MS/s CMOS Pipelined Analog-to-Digital Converter with Digital Background Calibration
    • May
    • H.-C. Liu, Z.-M. Lee, and J.-T. Wu, "A 15-b 40-MS/s CMOS Pipelined Analog-to-Digital Converter with Digital Background Calibration," IEEE J. Solid-State Circuits, vol. 40, no. 5, pp. 1047-1056, May 2005.
    • (2005) IEEE J. Solid-State Circuits , vol.40 , Issue.5 , pp. 1047-1056
    • Liu, H.-C.1    Lee, Z.-M.2    Wu, J.-T.3
  • 15
    • 2442676922 scopus 로고    scopus 로고
    • A 96dB SFDR 50MS/s Digitally Enhanced CMOS Pipeline A/D Converter,
    • Feb
    • K. Nair, and R. Harjani, "A 96dB SFDR 50MS/s Digitally Enhanced CMOS Pipeline A/D Converter, " IEEE ISSCC, Dig. Tech. Papers, 456- 539, Feb. 2004.
    • (2004) IEEE ISSCC, Dig. Tech. Papers , pp. 456-539
    • Nair, K.1    Harjani, R.2
  • 16
    • 8344221254 scopus 로고    scopus 로고
    • A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration
    • Nov
    • X. Wang, P. J. Hurst, and S. H. Lewis, "A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration," IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 1799-1808, Nov. 2004.
    • (2004) IEEE J. Solid-State Circuits , vol.39 , Issue.11 , pp. 1799-1808
    • Wang, X.1    Hurst, P.J.2    Lewis, S.H.3
  • 18
    • 34547296502 scopus 로고    scopus 로고
    • A 7.51mW, 11-bit Continuous-Time Sigma-Delta A/D Converter for WLAN Applications
    • May
    • R. Schoofs, M. Steyaert and W. Sansen, "A 7.51mW, 11-bit Continuous-Time Sigma-Delta A/D Converter for WLAN Applications," Proceedings of ISCAS 2006, pp. 4419-4422, May 2006.
    • (2006) Proceedings of ISCAS , pp. 4419-4422
    • Schoofs, R.1    Steyaert, M.2    Sansen, W.3
  • 19
    • 49549121624 scopus 로고    scopus 로고
    • A 28mW Spectrum-Sensing Reconfigurable 20MHz 72dB-SNR 70dB-SNDR DT Δσ ADC for 802.11n/WiMAX Receivers
    • Feb
    • P. Malla, H. Lakdawala, K. Kornegay and K. Soumyanath, "A 28mW Spectrum-Sensing Reconfigurable 20MHz 72dB-SNR 70dB-SNDR DT Δσ ADC for 802.11n/WiMAX Receivers," IEEE ISSCC, Dig. Tech. Papers, pp. 496-631, Feb. 2008.
    • (2008) IEEE ISSCC, Dig. Tech. Papers , pp. 496-631
    • Malla, P.1    Lakdawala, H.2    Kornegay, K.3    Soumyanath, K.4
  • 20
    • 28144464896 scopus 로고    scopus 로고
    • A 43mW CT Complex Δσ ADC with 23MHz of Signal Bandwidth and 68.8dB SNDR
    • Feb
    • N. Yaghini, and D. Johns, "A 43mW CT Complex Δσ ADC with 23MHz of Signal Bandwidth and 68.8dB SNDR," IEEE ISSCC, Dig. Tech. Papers, pp. 502-613, Feb. 2005.
    • (2005) IEEE ISSCC, Dig. Tech. Papers , pp. 502-613
    • Yaghini, N.1    Johns, D.2
  • 21
    • 0037630701 scopus 로고    scopus 로고
    • A 700/900mW/Channel CMOS Dual Analog Front-End IC for VDSL with Integrated 11.5/14.5dBm Line Drivers
    • Feb
    • M. Moyal, M. Groepl, H. Werker, G. Mitteregger, and J. Schambacher, "A 700/900mW/Channel CMOS Dual Analog Front-End IC for VDSL with Integrated 11.5/14.5dBm Line Drivers," IEEE ISSCC, Dig. Tech. Papers, pp. 416-504, Feb. 2003.
    • (2003) IEEE ISSCC, Dig. Tech. Papers , pp. 416-504
    • Moyal, M.1    Groepl, M.2    Werker, H.3    Mitteregger, G.4    Schambacher, J.5
  • 23
    • 64549098417 scopus 로고    scopus 로고
    • L. J. Breems, R. Rutten, R. van Veldhoven, G. van der Weidel and H. Termeer, A 56mW CT Quadrature Cascaded Δσ Modulator
    • L. J. Breems, R. Rutten, R. van Veldhoven, G. van der Weidel and H. Termeer, "A 56mW CT Quadrature Cascaded Δσ Modulator
  • 24
    • 64549117033 scopus 로고    scopus 로고
    • with 77dB DR in a Near Zero-IF 20MHz Band, IEEE ISSCC, Dig. Tech. Papers, pp. 238-599, Feb. 2007.
    • with 77dB DR in a Near Zero-IF 20MHz Band," IEEE ISSCC, Dig. Tech. Papers, pp. 238-599, Feb. 2007.
  • 25
    • 34548839092 scopus 로고    scopus 로고
    • A 0.13μm CMOS EDGE/UMTS/WLAN Tri-Mode Δσ ADC with -92dB THD
    • Feb
    • T. Christen, T. Burger, and Q. Huang, "A 0.13μm CMOS EDGE/UMTS/WLAN Tri-Mode Δσ ADC with -92dB THD," IEEE ISSCC, Dig. Tech. Papers, pp. 240-599, Feb. 2007.
    • (2007) IEEE ISSCC, Dig. Tech. Papers , pp. 240-599
    • Christen, T.1    Burger, T.2    Huang, Q.3
  • 27
    • 49549124516 scopus 로고    scopus 로고
    • A 65nm CMOS CT Modulator with 81dB DR and 8MHz BW Auto-Tuned by Pulse Injection
    • Feb
    • Y.-S. Shu, B.-S. Song, K. Bacranial, "A 65nm CMOS CT Modulator with 81dB DR and 8MHz BW Auto-Tuned by Pulse Injection," IEEE ISSCC, Dig. Tech. Papers, pp. 500-631, Feb. 2008.
    • (2008) IEEE ISSCC, Dig. Tech. Papers , pp. 500-631
    • Shu, Y.-S.1    Song, B.-S.2    Bacranial, K.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.