Contribution of interface states and oxide traps to the negative bias temperature instability of high-k pMOSFETs

IEEE Electron Device Letters

Volumn 30, Issue 3, 2009, Pages 291-293

  Jo, Minseok ^a   Chang, Man ^a   Kim, Seonghyun ^a   Jung, Hyung Suk ^b   Choi, Rino ^c   Hwang, Hyunsang ^a  

^a Gwangju Institute of Science and Technology (GIST)   (South Korea)

^b SAMSUNG Electronics   (South Korea)

^c Inha University   (South Korea)

Author keywords

Hafnium oxide; Interface states; Negative bias temperature instability (NBTI); Oxide traps

Indexed keywords

DIELECTRIC MATERIALS; GATE DIELECTRICS; GATES (TRANSISTOR); HAFNIUM; HAFNIUM COMPOUNDS; MOSFET DEVICES; NEGATIVE TEMPERATURE COEFFICIENT; OXIDES; PERSONAL DIGITAL ASSISTANTS;

DELAY-TIME; GENERATION RATES; HAFNIUM OXIDE; HIGH - K DIELECTRICS; INTERFACE STATES; MEASUREMENT TECHNIQUES; MEASUREMENT TIME; MOSFETS; NEGATIVE BIAS TEMPERATURE INSTABILITY (NBTI); OXIDE TRAPS; P-MOSFETS; POST-DEPOSITION ANNEALING;

THERMODYNAMIC STABILITY;

EID: 62549142283     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2008.2011926     Document Type: Article

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