Mitigating memory wall effects in high-clock-rate and multicore CMOS 3-D processor memory stacks

Proceedings of the IEEE

Volumn 97, Issue 1, 2009, Pages 108-122

  Jacob, Philip ^a   Zia, Aamir ^a   Erdogan, Okan ^a   Belemjian, Paul M ^a   Kim, Jin Woo ^a   Chu, Michael ^a   Kraft, Russell P ^a   McDonald, John F ^a   Bernstein, Kerry ^b  

^a RENSSELAER POLYTECHNIC INSTITUTE   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

3 D memory; Cache memories; Chip stacking; Memory wall; Multicore processors; Multithreading; Simulation

Indexed keywords

BUFFER STORAGE; CHIP SCALE PACKAGES; CLOCKS; CMOS INTEGRATED CIRCUITS; DATA TRANSFER; DATA TRANSFER RATES; ELECTROSTATIC DEVICES; MEMORY ARCHITECTURE; MULTITASKING; SI-GE ALLOYS;

CHIP STACKING; MEMORY WALL; MULTI-CORE PROCESSOR; MULTI-THREADING; SIMULATION;

CACHE MEMORY;

EID: 61549140973     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/JPROC.2008.2007472     Document Type: Article

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