Wafer-level 3D manufacturing issues for streaming video processors

IEEE International Symposium on Semiconductor Manufacturing Conference, Proceedings

Volumn , Issue , 2004, Pages 247-251

  Zeng, A Y ^a   Lu, J Q ^a   Gutmann, R J ^a   Rose, K ^a  

^a RENSSELAER POLYTECHNIC INSTITUTE   (United States)

Author keywords

High definition Television (HDTV); Streaming Video; Wafer level 3D Integration

Indexed keywords

BUFFER STORAGE; CAPACITANCE; CHEMICAL MECHANICAL POLISHING; CMOS INTEGRATED CIRCUITS; COPPER; DIELECTRIC DEVICES; ETCHING; GLUES; GLUING; HIGH DEFINITION TELEVISION; SILICON WAFERS; TECHNOLOGY TRANSFER;

DAMASCENE; NODES; STREAMING VIDEO; WAFER-LEVEL 3D INTEGRATION;

VIDEO SIGNAL PROCESSING;

EID: 4544378570     PISSN: 1523553X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

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