A 240-Mbps, 1-W CMOS EPRML read-channel LSI chip using an interleaved subranging pipeline A/D converter

IEEE Journal of Solid-State Circuits

Volumn 33, Issue 11, 1998, Pages 1840-1850

  Matsuura, Tatsuji ^a,b,c,d   Nara, Takashi ^a,e   Komatsu, Tatsuya ^a,f   Imaizumi, Eiki ^a,g,h,i   Matsutsuru, Toshihiro ^a,h   Horita, Ryutaro ^a,b,j   Katsu, Haruto ^a,k   Suzumura, Shintaro ^a,l,m   Sato, Kazuo ^a,n  

^a HITACHI LTD   (Japan)

^b IEEE   (Japan)

^c UNIVERSITY OF TOKYO   (Japan)

^d Institute of Electronics   (Japan)

^e TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

^f CHIBA INSTITUTE OF TECHNOLOGY   (Japan)

^g IBARAKI UNIVERSITY   (Japan)

^h TOKYO METROPOLITAN UNIVERSITY   (Japan)

ⁱ Hitachi ULSI Systems Inc   (Japan)

^j TOHOKU UNIVERSITY   (Japan)

^k HOSEI UNIVERSITY   (Japan)

^l Toyokawa Technical High School   (Japan)

^m IPSJ   (Japan)

ⁿ Toin Technical College   (Japan)

more..

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; HARD DISK STORAGE; INTEGRATED CIRCUIT LAYOUT; LSI CIRCUITS; PHASE LOCKED LOOPS;

ACQUISITION-MODE ANALOG PHASE LOCKED LOOPS (PLL); INTERLEAVED SUBRANGING PIPELINE ANALOG/DIGITAL CONVERTERS; READ/WRITE-CHANNEL LARGE SCALE INTEGRATION (LSI) CHIPS; TRACKING-MODE PRECISION DIGITAL PHASE LOCKED LOOPS (PLL);

MICROPROCESSOR CHIPS;

EID: 0032205464     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.726586     Document Type: Article

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