A 12b, 75MS/s pipelined ADC using incomplete settling

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2006, Pages 222-223

  Iroaga, Echere ^a   Murmann, Boris ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

Digital calibration; Digital correction; Open loop amplification and incomplete settling; Pipelined ADC

Indexed keywords

DIGITAL CALIBRATION; DIGITAL CORRECTION; OPEN LOOP AMPLIFICATION;

ENERGY DISSIPATION; POWER AMPLIFIERS; SOFTWARE PROTOTYPING;

ANALOG TO DIGITAL CONVERSION;

EID: 39749131698     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)