A 4.8-6.4 Gbps serial link for back-plane applications using decision feedback equalization

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2004, Pages 31-34

  Balan, Vishnu ^a   Caroselli, Joe ^a   Chem, Jenn Gang ^a   Desai, Chintan ^a   Liu, Cathy ^a  

^a AGERE SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; CMOS INTEGRATED CIRCUITS; DATA REDUCTION; ELECTRIC IMPEDANCE; EQUALIZERS; FIR FILTERS; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; NATURAL FREQUENCIES; PRINTED CIRCUIT BOARDS;

DECISION FEEDBACK EQUALIZATION; FEED FORWARD (FF); INCOMING SYMBOLS; INTER-SYMBOL INTERFERENCE (ISI);

INTEGRATED CIRCUITS;

EID: 17044432132     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. Alan Fiedler, Ross Mactaggart, James Welch, Shoba Krishnan, "A 1.0625 Gbps transceiver with 2X-oversampling and transmit signal preemphasis", ISSCC, vol. XL, pp. 238, Feb 1997.
2. Yoshiharu Kudoh, Muneo Fukaishi, Masayuki Mizuno, "A 0.13-μm CMOS 5-Gb/s 10-meter 28AWG Cable transceiver with no-feedback-loop continuous-time post-equalizer", Symp. VLSI Circuits Dig. 16, pp. 64-67, June 2002.
3. Sang-Hyun Lee Moon-Sang Hwang et al., "A 5Gb/s 0.25μm CMOS Jitter-tolerant variable-interval over sampling clock/Data recovery circuit", ISSCC, vol. XLV, pp. 256, Feb 2002.
4. nd ed., Kluwer Academic Publishers, 1993.