Equalization and Clock Recovery for a 2.5-10-Gb/s 2-PAM/4-PAM Backplane Transceiver Cell

IEEE Journal of Solid-State Circuits

Volumn 38, Issue 12, 2003, Pages 2121-2130

  Zerbe, Jared L ^a   Werner, Carl W ^a   Stojanovic, Vladimir ^a   Chen, Fred ^a   Wei, Jason ^a   Tsang, Grace ^a   Kim, Dennis ^a   Stonecypher, William F ^a   Ho, Andrew ^a   Thrush, Timothy P ^a   Kollipara, Ravi T ^a   Donnelly, Kevin S ^a   Horowitz, Mark A ^b  

^a RAMBUS INC   (United States)

^b STANFORD UNIVERSITY   (United States)

Author keywords

Adaptive equalizers; Decision feedback equalizers; Multilevel systems; Pulse amplitude modulation; SerDes; Serial links; Transceivers

Indexed keywords

DECISION FEEDBACK EQUALIZERS; ELECTRIC IMPEDANCE; ERROR ANALYSIS; OPTIMIZATION; PROBABILITY DISTRIBUTIONS; PULSE AMPLITUDE MODULATION; REFLECTION; SIGNAL PROCESSING; TRANSMITTERS;

ADAPTIVE EQUALIZERS; CLOCK RECOVERY; MULTILEVEL SYSTEMS; SERIAL LINKS;

TRANSCEIVERS;

EID: 9144245616     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2003.818572     Document Type: Conference Paper

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