Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 592-595

  Ghoneima, Maged ^a   Ismail, Yehea ^a   Khellah, Muhammad ^b   Tschanz, James ^b   Ye, Yibin ^b   De, Vivek ^b  

^a NORTHWESTERN UNIVERSITY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUS ARCHITECTURE; COUPLING CAPACITANCE; CYCLE TIME; DELAY-SLACK; FORWARD BODY BIAS; MAXIMUM DISTANCE; ON-CHIP BUS; POWER DISSIPATION; PROPOSED ARCHITECTURES;

ELECTRON ENERGY LOSS SPECTROSCOPY; ENERGY DISSIPATORS;

ENERGY DISSIPATION;

EID: 61349164260     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1464657     Document Type: Conference Paper

References (11)

1. Y. Shin and T. Sakurai, "Coupling-Driven Bus Design for Low-Power Application-Specific Sys.," In DAC'01,pp. 750-753, 2001
2. ® 4 Processor," Intel Technology Journal,Ql, 2001
3. P. Sotiriadis and A. Chandrakasan., "A bus energy model for deep submicron technology," T-VLSI,vol.10-3, pp. 341-350, June 2002.
4. K Hirose and H. Yasuura, "A Bus Delay Reduction Technique Considering Crosstalk," Proceedings. Design, Automation and Test in Europe Conference,pp. 441-445, 2000.
5. K. Nose and T. Sakurai, "Two schemes to reduce interconnect delay in bi-directional and uni-directional buses," VLSI Circuit Symposium 2001,pp. 193-194, 2001.
6. M. Khellah, J. Tscahnz, Y. Ye, S. Narendra and V. De, "Static Pulsed Bus for On-Chip Interconnects," In VLSI Symposium,pp. 78-79, June 2002.
7. K-W Kim, S-0 Jung, T. Kim, P. Saxena, C. Liu, and S-M Kang, "Coupling delay optimization by temporal decorrelation using dual threshold voltage technology," IEEE Trans. On VLSI Systems,vol. 11, No.5, October 2003, pp. 879-887.
8. U. Ko, A. Pua, A. Hill, and P. Srivastava, "Hybrid dual-threshold design techniques for high-performance processors with low-power features," ISLPED,pp. 307-311, August 1997
9. T. Karnik, et al, "Total power optimization by simultaneous dual- Vt allocation and device sizing in high performance microprocessors ", IEEE/ACMDAC,pp.486-491, June, 2002.
10. S. Narendra, A. Keshavarzi, B. Bloechel, S. Borkar, and V. De, "Forward Body Bias for Microprocessors in 130nm technology generation and beyond," IEEE Journal of Solid State Circuits, vol. 38, no.5, pp. 696-701, May 2003.
11. K Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, "Leakage current mechanisms and leakage reduction techniques in deep-submicron CMOS circuits," Proceedings of the IEEE,Feb. 2003