CuNoC: A dynamic scalable communication structure for dynamically reconfigurable FPGAs

Microprocessors and Microsystems

Volumn 33, Issue 1, 2009, Pages 24-36

  Jovanovic S ^a   Tanougast, C ^a   Bobda, C ^b   Weber, S ^a  

^a UNIVERSITÉ DE LORRAINE   (France)

^b University of Koblenz Landau   (Germany)

Author keywords

Dynamic placement of modules; FPGAs; Network on chip (NoCs); Partial reconfiguration; Reconfigurable devices

Indexed keywords

ADAPTIVE ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; BIOLOGICAL MATERIALS; COMMUNICATION; ELECTRIC NETWORK TOPOLOGY; INTEGRATED CIRCUITS; LARGE SCALE SYSTEMS; ROUTING ALGORITHMS;

DYNAMIC PLACEMENT OF MODULES; FPGAS; NETWORK-ON-CHIP (NOCS); PARTIAL RECONFIGURATION; RECONFIGURABLE DEVICES;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 60049093242     PISSN: 01419331     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.micpro.2008.08.004     Document Type: Article

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