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Volumn 22, Issue 5, 2005, Pages 443-451

Dynamic interconnection of reconfigurable modules on reconfigurable devices

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BUFFER STORAGE; FIELD PROGRAMMABLE GATE ARRAYS; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; ROUTERS;

EID: 27344453831     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2005.109     Document Type: Article
Times cited : (74)

References (10)
  • 2
    • 0347566174 scopus 로고    scopus 로고
    • "Online Scheduling and Placement of Real-Time Tasks to Partially Reconfigurable Devices"
    • IEEE CS Press
    • C. Steiger et al., "Online Scheduling and Placement of Real-Time Tasks to Partially Reconfigurable Devices," Proc. 24th Int'l Real-Time Systems Symp. (RTSS 03), IEEE CS Press, 2003, pp. 224-235.
    • (2003) Proc. 24th Int'l Real-Time Systems Symp. (RTSS 03) , pp. 224-235
    • Steiger, C.1
  • 4
    • 84947932382 scopus 로고    scopus 로고
    • "A Dynamic NoC Approach for Communication in Reconfigurable Devices"
    • LNCS, Springer
    • C. Bobda et al., "A Dynamic NoC Approach for Communication in Reconfigurable Devices," Proc. 14th Int'l Field-Programmable Logic Conf. (FPL 04), LNCS vol. 3203, Springer, 2004, pp. 1032-1036.
    • (2004) Proc. 14th Int'l Field-Programmable Logic Conf. (FPL 04) , vol.3203 , pp. 1032-1036
    • Bobda, C.1
  • 5
    • 35248833754 scopus 로고    scopus 로고
    • "Networks on Chip as Hardware Components of an OS for Reconfigurable Systems"
    • LNCS, Springer
    • T. Marescaux et al., "Networks on Chip as Hardware Components of an OS for Reconfigurable Systems," Proc. 13th Int'l Field-Programmable Logic Conf. (FPL 03), LNCS vol. 2778, Springer, 2003, pp. 595-605.
    • (2003) Proc. 13th Int'l Field-Programmable Logic Conf. (FPL 03) , vol.2778 , pp. 595-605
    • Marescaux, T.1
  • 7
    • 0042522917 scopus 로고    scopus 로고
    • "Pact XPPA Self-Reconfigurable Data Processing Architecture"
    • Sept.
    • V. Baumgarte et al., "Pact XPPA Self-Reconfigurable Data Processing Architecture," J. Supercomputing, vol. 26, no. 2, Sept. 2003, pp. 167-184.
    • (2003) J. Supercomputing , vol.26 , Issue.2 , pp. 167-184
    • Baumgarte, V.1
  • 8
    • 0036149420 scopus 로고    scopus 로고
    • "Networks on Chips: A New SoC Paradigm"
    • Jan.
    • L. Benini and G. Micheli, "Networks on Chips: A New SoC Paradigm," Computer, vol. 35, no. 1, Jan. 2001, pp. 70-78.
    • (2001) Computer , vol.35 , Issue.1 , pp. 70-78
    • Benini, L.1    Micheli, G.2
  • 9
    • 0006366481 scopus 로고    scopus 로고
    • "Network on Chip: An Architecture for Billion Transistor Era"
    • IEEE Press
    • A. Hemani et al., "Network on Chip: An Architecture for Billion Transistor Era," Proc. 18th Int'l Norchip Conf., IEEE Press, 2000, pp. 166-173.
    • (2000) Proc. 18th Int'l Norchip Conf. , pp. 166-173
    • Hemani, A.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.