-
1
-
-
0036149420
-
Networks on chips: A new SoC paradigm
-
Jan
-
L. Benini and G. D. Micheli, "Networks on chips: a new SoC paradigm," in IEEE Computer, Jan. 2002.
-
(2002)
IEEE Computer
-
-
Benini, L.1
Micheli, G.D.2
-
2
-
-
0006366481
-
Network on chip: An architecture for billion transistor era
-
Sept
-
A. Hemani, A. Jantsch, S. Kumar, A. Postula, J. Oberg, and D. Lindqvist, "Network on chip: An architecture for billion transistor era," in Proc. of the International NorChip Conference, Sept. 2000.
-
(2000)
Proc. of the International NorChip Conference
-
-
Hemani, A.1
Jantsch, A.2
Kumar, S.3
Postula, A.4
Oberg, J.5
Lindqvist, D.6
-
3
-
-
84893687806
-
A generic architecture for on-chip packet-switched interconnections
-
Mar
-
P. Guerrier and A. Greiner, "A generic architecture for on-chip packet-switched interconnections," in Proc. Design and Test in Europe (DATE), Mar. 2000, pp. 250-256.
-
(2000)
Proc. Design and Test in Europe (DATE)
, pp. 250-256
-
-
Guerrier, P.1
Greiner, A.2
-
4
-
-
84948696213
-
-
S. K. et al, A network on chip architecture and design methodology, in Proc. IEEE Computer Society Annual Symp. on VLSI, 2002, pp. 117-124.
-
S. K. et al, "A network on chip architecture and design methodology," in Proc. IEEE Computer Society Annual Symp. on VLSI, 2002, pp. 117-124.
-
-
-
-
5
-
-
0034848112
-
Route packets, not wires: On-chip interconnection networks
-
W. J. Dally and B. Towles, "Route packets, not wires: On-chip interconnection networks," in Proc. Design Automation Conf. (DAC), 2001, pp. 683-689.
-
(2001)
Proc. Design Automation Conf. (DAC)
, pp. 683-689
-
-
Dally, W.J.1
Towles, B.2
-
6
-
-
0036760592
-
An interconnect architecture for networking systems on chips
-
Mar
-
F. Kaiim and et al, "An interconnect architecture for networking systems on chips," IEEE Micro, vol. 22, no. 5, pp. 36-45, Mar. 2002.
-
(2002)
IEEE Micro
, vol.22
, Issue.5
, pp. 36-45
-
-
Kaiim, F.1
and et, al.2
-
7
-
-
0038420731
-
Design of a switch for network on chip applications
-
May
-
P. P. Pande, C. Grecu, A. Ivanov, and R. Saleh, "Design of a switch for network on chip applications," in Proc. Int. Symp. Circuits and Systems (ISCAS), vol. 5, May 2003. pp. 217-220.
-
(2003)
Proc. Int. Symp. Circuits and Systems (ISCAS)
, vol.5
, pp. 217-220
-
-
Pande, P.P.1
Grecu, C.2
Ivanov, A.3
Saleh, R.4
-
8
-
-
24144461667
-
Performance evaluation and design trade-offs for network-on-chip interconnect architectures
-
Aug
-
P. P. Pande, C. Grecu, M. Jones, A. Ivanov, and R. Saleh, "Performance evaluation and design trade-offs for network-on-chip interconnect architectures," IEEE Trans. Comput, vol. 54, no. 8, pp. 1025-1040, Aug. 2005.
-
(2005)
IEEE Trans. Comput
, vol.54
, Issue.8
, pp. 1025-1040
-
-
Pande, P.P.1
Grecu, C.2
Jones, M.3
Ivanov, A.4
Saleh, R.5
-
9
-
-
33746922011
-
Dynoc: A dynamic infrastructure for communication in dynamically reconfigurable devices
-
Aug
-
C. Bobda, A. Ahmadinia, M. Majer, J. Teich, S. Fekete, and J. van der Veen, "Dynoc: A dynamic infrastructure for communication in dynamically reconfigurable devices," in International Conf. on FPL, Aug. 2005.
-
(2005)
International Conf. on FPL
-
-
Bobda, C.1
Ahmadinia, A.2
Majer, M.3
Teich, J.4
Fekete, S.5
van der Veen, J.6
-
10
-
-
33746318155
-
Packet routing in dynamically changing networks on chip
-
Apr
-
M. Majer, C. Bobda, A. Ahmadinia, and J. Teich, "Packet routing in dynamically changing networks on chip," in Proc. of 19th IEEE International Parallel and Distributed Symposium, Apr. 2005.
-
(2005)
Proc. of 19th IEEE International Parallel and Distributed Symposium
-
-
Majer, M.1
Bobda, C.2
Ahmadinia, A.3
Teich, J.4
-
11
-
-
27344453831
-
Dynamic interconnection of reconfigurable modules on reconfigurable devices
-
Sept
-
C. Bobda and A. Ahmadinia, "Dynamic interconnection of reconfigurable modules on reconfigurable devices," in Design & Test of Computers, IEEE, vol. 22, Sept. 2005, pp. 443-451.
-
(2005)
Design & Test of Computers, IEEE
, vol.22
, pp. 443-451
-
-
Bobda, C.1
Ahmadinia, A.2
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