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Volumn , Issue , 2007, Pages 753-756

CuNoC: A scalable dynamic NoC for dynamically reconflgurable FPGAs

Author keywords

[No Author keywords available]

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 44649182862     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2007.4380761     Document Type: Conference Paper
Times cited : (33)

References (11)
  • 1
    • 0036149420 scopus 로고    scopus 로고
    • Networks on chips: A new SoC paradigm
    • Jan
    • L. Benini and G. D. Micheli, "Networks on chips: a new SoC paradigm," in IEEE Computer, Jan. 2002.
    • (2002) IEEE Computer
    • Benini, L.1    Micheli, G.D.2
  • 3
    • 84893687806 scopus 로고    scopus 로고
    • A generic architecture for on-chip packet-switched interconnections
    • Mar
    • P. Guerrier and A. Greiner, "A generic architecture for on-chip packet-switched interconnections," in Proc. Design and Test in Europe (DATE), Mar. 2000, pp. 250-256.
    • (2000) Proc. Design and Test in Europe (DATE) , pp. 250-256
    • Guerrier, P.1    Greiner, A.2
  • 4
    • 84948696213 scopus 로고    scopus 로고
    • S. K. et al, A network on chip architecture and design methodology, in Proc. IEEE Computer Society Annual Symp. on VLSI, 2002, pp. 117-124.
    • S. K. et al, "A network on chip architecture and design methodology," in Proc. IEEE Computer Society Annual Symp. on VLSI, 2002, pp. 117-124.
  • 5
    • 0034848112 scopus 로고    scopus 로고
    • Route packets, not wires: On-chip interconnection networks
    • W. J. Dally and B. Towles, "Route packets, not wires: On-chip interconnection networks," in Proc. Design Automation Conf. (DAC), 2001, pp. 683-689.
    • (2001) Proc. Design Automation Conf. (DAC) , pp. 683-689
    • Dally, W.J.1    Towles, B.2
  • 6
    • 0036760592 scopus 로고    scopus 로고
    • An interconnect architecture for networking systems on chips
    • Mar
    • F. Kaiim and et al, "An interconnect architecture for networking systems on chips," IEEE Micro, vol. 22, no. 5, pp. 36-45, Mar. 2002.
    • (2002) IEEE Micro , vol.22 , Issue.5 , pp. 36-45
    • Kaiim, F.1    and et, al.2
  • 8
    • 24144461667 scopus 로고    scopus 로고
    • Performance evaluation and design trade-offs for network-on-chip interconnect architectures
    • Aug
    • P. P. Pande, C. Grecu, M. Jones, A. Ivanov, and R. Saleh, "Performance evaluation and design trade-offs for network-on-chip interconnect architectures," IEEE Trans. Comput, vol. 54, no. 8, pp. 1025-1040, Aug. 2005.
    • (2005) IEEE Trans. Comput , vol.54 , Issue.8 , pp. 1025-1040
    • Pande, P.P.1    Grecu, C.2    Jones, M.3    Ivanov, A.4    Saleh, R.5
  • 11
    • 27344453831 scopus 로고    scopus 로고
    • Dynamic interconnection of reconfigurable modules on reconfigurable devices
    • Sept
    • C. Bobda and A. Ahmadinia, "Dynamic interconnection of reconfigurable modules on reconfigurable devices," in Design & Test of Computers, IEEE, vol. 22, Sept. 2005, pp. 443-451.
    • (2005) Design & Test of Computers, IEEE , vol.22 , pp. 443-451
    • Bobda, C.1    Ahmadinia, A.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.