A 3.8 GHz 153 Mb SRAM design with dynamic stability enhancement and leakage reduction in 45 nm high-k metal gate CMOS technology

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 1, 2009, Pages 148-154

  Hamzaoglu, Fatih ^a   Zhang, Kevin ^a   Wang, Yih ^a   Ahn, Hong Jo ^a   Bhattacharya, Uddalak ^a   Chen, Zhanping ^a   Ng, Yong Gee ^a   Pavlov, Andrei ^a   Smits, Ken ^a   Bohr, Mark ^a  

^a INTEL CORPORATION   (United States)

Author keywords

Forward body bias; High speed; Leakage reduction; Low power; Sleep transistor; Static random access memory(SRAM)

Indexed keywords

CMOS INTEGRATED CIRCUITS; LOGIC DESIGN; SLEEP RESEARCH; TRANSISTORS;

FORWARD-BODY-BIAS; HIGH-SPEED; LEAKAGE REDUCTION; LOW-POWER; SLEEP TRANSISTOR; STATIC-RANDOM-ACCESS-MEMORY(SRAM);

STATIC RANDOM ACCESS STORAGE;

EID: 58149263242     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.2007151     Document Type: Conference Paper

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