Penryn: 45-nm next generation Intel® Core™ 2 processor

2007 IEEE Asian Solid-State Circuits Conference, A-SSCC

Volumn , Issue , 2007, Pages 14-17

  George, Varghese ^a   Jahagirdar, Sanjeev ^a   Tong, Chao ^a   Smits, Ken ^a   Damaraju, Satish ^a   Siers, Scott ^a   Naydenov, Ves ^a   Khondker, Tanveer ^a   Sarkar, Sanjib ^a   Singh, Puneet ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

L2 CACHE; MARKET SEGMENTS; MICRO ARCHITECTURES; SOLID-STATE CIRCUITS CONFERENCE;

MICROPROCESSOR CHIPS;

EID: 51349166333     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2007.4425784     Document Type: Conference Paper

References (4)

1. S. Rusu, S. Tam, H. Muljono, D. Ayers, J. Chang, B. Cherkauer, J. Stinson, J. Benoit, R. Varada, J. Leung, R. Limaye, S. Vora "A 65-nm Dual-Core Multi-Threaded Xeon™ Processor with 16MB L3 Cache", ISSCC, 2007
2. N. Sakran, M. Yuffe, M. Mehalel, J. Doweck, E. Knoll, A. Kovacs, "The implementation of the 65nm Dual core 64b Merom Processor" ISSCC 2007 Digest Section 5.6
3. K. Zhang, et al., "A SRAM Design on 65nm CMOS Technology with Integrated Leakage Reduction Scheme," VLSI Circuit Symposium, Digest of Tech. Papers, pp. 294-295, June 2004.
4. http://download.intel.com/technology/architecture/new-instructions-paper. pdf