Operating-margin-improved SRAM with column-at-a-time body-bias control technique

ESSCIRC 2007 - Proceedings of the 33rd European Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 396-399

  Yamaoka, Masanao ^a   Kawahara, Takayuki ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COLUMNS (STRUCTURAL);

(+ MOD 2N) OPERATION; BODY BIAS CONTROL; BODY BIASING; EUROPEAN; OPERATING MARGINS; PROTOTYPE CHIPS; SOLID-STATE CIRCUITS CONFERENCE; SRAM MEMORY CELLS;

STATIC RANDOM ACCESS STORAGE;

EID: 44849096289     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2007.4430326     Document Type: Conference Paper

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7. M. Yamaoka et al., IEEE ISSCC, Feb. 2004, pp 494-495.