Row-by-row dynamic source-line voltage control (RRDSV) scheme for two orders of magnitude leakage current reduction of sub-1-V-VDD SRAM's

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn 2003-January, Issue , 2003, Pages 66-71

  Min, Kyeong Sik ^a,b   Kanda, K ^a,c   Sakurai, T ^a  

^a INSTITUTE OF INDUSTRIAL SCIENCE   (Japan)

^b Kookmin University   (South Korea)

^c FUJITSU LABORATORIES LTD   (Japan)

Author keywords

CMOS technology; Degradation; Industrial control; Laboratories; Leakage current; Permission; Random access memory; Subthreshold current; Threshold voltage; Voltage control

Indexed keywords

CMOS INTEGRATED CIRCUITS; DEGRADATION; LABORATORIES; LEAKAGE CURRENTS; LOW POWER ELECTRONICS; POWER ELECTRONICS; RANDOM ACCESS STORAGE; THRESHOLD VOLTAGE; VOLTAGE CONTROL;

CMOS TECHNOLOGY; INDUSTRIAL CONTROLS; PERMISSION; RANDOM ACCESS MEMORY; SUB-THRESHOLD CURRENT;

STATIC RANDOM ACCESS STORAGE;

EID: 1542359179     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/LPE.2003.1231837     Document Type: Conference Paper

References (9)

1. International Technology Roadmap for Semiconductors (ITRS99)
2. T. Sakurai, "Perspectives on power-aware electronics," Digest of IEEE International Solid-State Circuits Conference, pp. 26-29, Feb. 2003.
3. K. Kanda, T. Miyazaki, K. Min, H. Kawaguchi, and T. Sakurai, "Two Orders of Magnitude Reduction of Low Voltage SRAM's by Row-by-Row Dynamic VDD Control (RDDV) Scheme," Proceedings of IEEE International ASIC/SOC Conference, pp. 381-385, Rochester in USA, Sep. 2002.
4. A. Agarwal, H. Li, and K. Roy, "A single Vt low-leakage gated-ground cache for deep submicron," IEEE Journal of Solid-State Circuits, vol. 38, no. 2, pp. 319-328, 2003.
5. H. Kawaguchi, Y. Iataka, and T. Sakurai, "Dynamic leakage cut-off scheme for low-voltage SRAM's," Technical digest of Symposium on VLSI circuits, pp. 140-141, June, 1998.
6. H. Mizuno and T. Nagano, "Driving source-line cell architecture for sub-1-V high-speed low-power applications," IEEE Journal of Solid-State Circuits, vol. 31, no. 4, pp. 552-557, April 1996.
7. K. Osada, Y. Saitoh, E. Ibe, and K. Ishibashi, "16.7fA/cell tunnel-leakage-suppressed 16Mb SRAM for handling cosmic-ray-induced multi-errors," IEEE International Solid-State Circuits Conference, pp. 302-303, 2003.
8. K. Agawa, H. Hara, T. Takayanagi, and T. Kuroda, "A bit line leakage compensation scheme for low-voltage SRAM's," IEEE Journal of Solid-State Circuits, vol. 36, no. 5, pp. 726-734, 2001.
9. Berkeley predictive technology model web site: http://www-device.eecs.berkeley.edu/~ptm