메뉴 건너뛰기




Volumn , Issue , 2008, Pages 1171-1174

Configuration of floorplan and placement algorithm using horizontal and vertical contour based on single sequence

Author keywords

[No Author keywords available]

Indexed keywords

FAST DECODING; GEOMETRICAL INFORMATIONS; LINEAR TIMES; MCNC BENCHMARKS; PLACEMENT ALGORITHMS; SINGLE SEQUENCES;

EID: 58149159197     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCCAS.2008.4657975     Document Type: Conference Paper
Times cited : (4)

References (20)
  • 3
    • 0030378255 scopus 로고    scopus 로고
    • VLSI Module Placement Based on Rectangle-packing by the Sequence-Pair
    • H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani, "VLSI Module Placement Based on Rectangle-packing by the Sequence-Pair", IEEE Trans. CAD, Vol. 15, No. 12, pp. 1518-1524, 1996.
    • (1996) IEEE Trans. CAD , vol.15 , Issue.12 , pp. 1518-1524
    • Murata, H.1    Fujiyoshi, K.2    Nakatake, S.3    Kajitani, Y.4
  • 4
    • 0030408582 scopus 로고    scopus 로고
    • Module Placement on BSG-Structure and IC Layout Applications
    • Nov
    • S. Nakatake, K. Fujiyoshi, H. Murata and Y. Kajitani, "Module Placement on BSG-Structure and IC Layout Applications", Proc. ICCAD, pp. 484-451, Nov. 1996.
    • (1996) Proc. ICCAD , pp. 484-451
    • Nakatake, S.1    Fujiyoshi, K.2    Murata, H.3    Kajitani, Y.4
  • 5
    • 0003090754 scopus 로고    scopus 로고
    • An O-Tree Representation of Non-Slicing Floorplan and Its Applications
    • Jun
    • P. N. Guo, C. K. Cheng, and T. Yoshimura, "An O-Tree Representation of Non-Slicing Floorplan and Its Applications", Proc. 36th DAC, pp. 286-291, Jun., 1999.
    • (1999) Proc. 36th DAC , pp. 286-291
    • Guo, P.N.1    Cheng, C.K.2    Yoshimura, T.3
  • 6
    • 0033701594 scopus 로고    scopus 로고
    • B*-trees: A New Representation for Non-Slicing Floorplans
    • LA, CA, June
    • Y. C. Chang, Y. W. Chang, G.-M. Wu, and S.-W. Wu, "B*-trees: A New Representation for Non-Slicing Floorplans", Proc. 37th DAC, pp. 458-463, LA, CA, June 2000.
    • (2000) Proc. 37th DAC , pp. 458-463
    • Chang, Y.C.1    Chang, Y.W.2    Wu, G.-M.3    Wu, S.-W.4
  • 7
    • 0034481271 scopus 로고    scopus 로고
    • Corner Block List: An Efficient Topological Representation of Non-Slicing Floorplan in Proc
    • Nov
    • X. Hong, S. Dong, Y. Ma, Y. Cai, C. K. Cheng, and J. Gu, "Corner Block List: An Efficient Topological Representation of Non-Slicing Floorplan" in Proc. ICCAD 2000, pp. 8-12, Nov., 2000.
    • (2000) ICCAD 2000 , pp. 8-12
    • Hong, X.1    Dong, S.2    Ma, Y.3    Cai, Y.4    Cheng, C.K.5    Gu, J.6
  • 8
    • 0034855935 scopus 로고    scopus 로고
    • J.-M Lin and Y.-W Chang, TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans, Proc. DAC, pp.764-769, 2001.
    • J.-M Lin and Y.-W Chang, "TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans", Proc. DAC, pp.764-769, 2001.
  • 10
    • 0141750617 scopus 로고    scopus 로고
    • Corner Sequence - A P-Admissible Floorplan Representation With a Worst Case Linear-Time Packing Scheme
    • AUGUST
    • Jai-Ming Lin, Yao-Wen Chang, and Shih-Ping Lin, "Corner Sequence - A P-Admissible Floorplan Representation With a Worst Case Linear-Time Packing Scheme", IEEE TRANS. ON VLI (VLSI) SYST, VOL. 11, NO. 4. pp. 679-685, AUGUST 2003.
    • (2003) IEEE TRANS. ON VLI (VLSI) SYST , vol.11 , Issue.4 , pp. 679-685
    • Lin, J.-M.1    Chang, Y.-W.2    Lin, S.-P.3
  • 11
    • 58149152064 scopus 로고    scopus 로고
    • The Single Sequence That Unifies Placement and Floorplanning
    • Asian Semi-Conductor University Cooperations, January
    • Y. Kajitani, "The Single Sequence That Unifies Placement and Floorplanning", presented at the presession meeting of ASP-DAC, 2003, "Asian Semi-Conductor University Cooperations", January 2003.
    • (2003) presented at the presession meeting of ASP-DAC
    • Kajitani, Y.1
  • 13
    • 4344611654 scopus 로고    scopus 로고
    • Theory of T-junction foorplans in terms of single-sequence
    • Vancouver, Canada
    • X. Zhang and Y. Kajitani, "Theory of T-junction foorplans in terms of single-sequence", IEEE Int. Symp. on Circuits and Systems, Vancouver, Canada. 2004, pp. 341-344.
    • (2004) IEEE Int. Symp. on Circuits and Systems , pp. 341-344
    • Zhang, X.1    Kajitani, Y.2
  • 14
    • 11244302681 scopus 로고    scopus 로고
    • A normalized configuration of foorplans and ABLR-relations, International Confeference on Communications
    • Chengdu, China
    • X. Zhang and Y. Kajitani, "A normalized configuration of foorplans and ABLR-relations", International Confeference on Communications, Circuits and Systems, Chengdu, China. 2004, pp. 1218-1222.
    • (2004) Circuits and Systems , pp. 1218-1222
    • Zhang, X.1    Kajitani, Y.2
  • 16
    • 11244331754 scopus 로고    scopus 로고
    • X. Zhu, C. Zhuang, and Y. Kajitani, A general packing algorithm based on single-sequence, ICCCAS 2004, Chengdu, China, pp. 1257-1261, 2004.
    • X. Zhu, C. Zhuang, and Y. Kajitani, "A general packing algorithm based on single-sequence", ICCCAS 2004, Chengdu, China, pp. 1257-1261, 2004.
  • 17
    • 84962213117 scopus 로고    scopus 로고
    • Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks, Proc
    • Y. Ma, X. Hong, S. Dong, Y. Cai, C.K. Cheng, J. Gu, "Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks", Proc. ASP-DAC 2002, pp.387-392, 2002.
    • (2002) ASP-DAC 2002 , pp. 387-392
    • Ma, Y.1    Hong, X.2    Dong, S.3    Cai, Y.4    Cheng, C.K.5    Gu, J.6
  • 18
    • 2442582530 scopus 로고    scopus 로고
    • Space-Planning: Placement of Modules with Controlled Empty Area by Single-Sequence, Proc
    • Jan
    • X. Zhang, Y. Kajitani, "Space-Planning: Placement of Modules with Controlled Empty Area by Single-Sequence", Proc. ASP-DAC 2004, pp. 25-30, Jan.2004.
    • (2004) ASP-DAC 2004 , pp. 25-30
    • Zhang, X.1    Kajitani, Y.2
  • 19
    • 85085516049 scopus 로고    scopus 로고
    • Layer Based Area Partition Using Single-Sequence for Preferable Routes
    • X. Zhang, X. Zhu, Y. Kajitani, "Layer Based Area Partition Using Single-Sequence for Preferable Routes", Proc. ASICON 2003, pp. 109-112, 2003.
    • (2003) Proc. ASICON 2003 , pp. 109-112
    • Zhang, X.1    Zhu, X.2    Kajitani, Y.3
  • 20
    • 0034823712 scopus 로고    scopus 로고
    • Revisiting floorplan representations
    • June
    • B. Yao, C-K Cheng, and R. Graham, "Revisiting floorplan representations", ISPD 2001, pp. 138-143, June 2001.
    • (2001) ISPD 2001 , pp. 138-143
    • Yao, B.1    Cheng, C.-K.2    Graham, R.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.