Theory of T-junction floorplans in terms of single-sequence

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 2004, Pages

  Zhang, Xuliang ^a,b   Kajitani, Yoji ^b  

^a SII NANOTECHNOLOGY INC   (Japan)

^b UNIVERSITY OF KITAKYUSHU   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

PHYSICAL DESIGN; ROUTABILITY; SYSTEM CHIPS;

ALGORITHMS; COMPUTATIONAL COMPLEXITY; CONSTRAINT THEORY; ENCODING (SYMBOLS); MICROPROCESSOR CHIPS; OPTIMIZATION; TOPOLOGY;

SEMICONDUCTOR JUNCTIONS;

EID: 4344611654     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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