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1
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58149152064
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The single sequence that unifies placement and floorplanning
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"Asian Semi-Conductor University Cooperations", January, 2003
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Y. Kajitani, "The Single Sequence That Unifies Placement and Floorplanning", presented at the presession meeting of ASP-DAC, 2003, "Asian Semi-Conductor University Cooperations", January, 2003.
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(2003)
Presession Meeting of ASP-DAC
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Kajitani, Y.1
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2
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0030408582
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Module placement on BSG-structure and IC layout applications
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S. Nakatake, K. Fujiyoshi, H. Murata and Y. Kajitani, "Module Placement on BSG-Structure and IC Layout Applications", ICCAD 1996, pp.484-451
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ICCAD 1996
, pp. 484-451
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Nakatake, S.1
Fujiyoshi, K.2
Murata, H.3
Kajitani, Y.4
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3
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0037667661
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March
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K. Sakanushi, Y. Kajitani, and D. P. Mehta, "The Quarter-State-Sequence Floorplan Representation, IEEE Tractions On Circuits and Systems-I: Fundamental Theory and Applications", Vol. 50, No. 3, March 2003
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(2003)
The Quarter-state-sequence Floorplan Representation, IEEE Tractions on Circuits and Systems-I: Fundamental Theory and Applications
, vol.50
, Issue.3
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Sakanushi, K.1
Kajitani, Y.2
Mehta, D.P.3
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4
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11244352347
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A new floorplanning by HPG: Halmiton path-based graph representation
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Changwen, Y. Kajitani, "A New Floorplanning by HPG: Halmiton Path-based Graph Representation", ASICON 2003, pp. 174-177
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ASICON 2003
, pp. 174-177
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Changwen1
Kajitani, Y.2
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5
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0009554967
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Covering the square by squares without overlapping
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in Japanese
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M. Abe, "Covering The Square by Squares without Overlapping", Journal of Japan Mathematical Physics, Vol.4, No. 4, pp. 359-366, 1930 (in Japanese)
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Abe, M.1
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6
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85040657895
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A new algorithm for floorplan designs
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D. F. Wong, and C. L. Liu, "A New Algorithm for Floorplan Designs", 23rd DAC, pp.101-107, 1986.
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(1986)
23rd DAC
, pp. 101-107
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Wong, D.F.1
Liu, C.L.2
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7
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0003090754
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An O-tree representation of non-slicing floorplan and its applications
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Jun.
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P. N. Guo, C. K. Cheng, and T. Yoshimura, "An O-Tree Representation of Non-Slicing Floorplan and Its Applications", 36th DAC, pp.286-291, Jun., 1999.
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(1999)
36th DAC
, pp. 286-291
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Guo, P.N.1
Cheng, C.K.2
Yoshimura, T.3
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8
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2342508075
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A general and fast floorplaning by reduct-seq representation
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VLD2000-24
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K. Sakanushi, K. Midorikawa, and Y. Kajitani, "A General and Fast Floorplaning by Reduct-Seq Representation", Technical Report of IEICE, (VLD2000-24), Vol.100, No.120, pp.109-116, 2000.
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(2000)
Technical Report of IEICE
, vol.100
, Issue.120
, pp. 109-116
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Sakanushi, K.1
Midorikawa, K.2
Kajitani, Y.3
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9
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0025564843
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A theory of rectangular dual graphs
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Y-T. Lai and M. Leiwand, "A Theory of Rectangular Dual Graphs", Algorithmica, Vol.5, pp. 467-483, 1990.
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Algorithmica
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Lai, Y.-T.1
Leiwand, M.2
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10
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0344017702
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An enhanced Q-sequence augmented with essential empty room insertions and parenthesis trees
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C. Zhuang, K. Sakanushi, L. Jin and Y. Kajitani, "An Enhanced Q-Sequence Augmented with Essential Empty Room Insertions and Parenthesis Trees", DATE 2002, pp.61-68
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DATE 2002
, pp. 61-68
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Zhuang, C.1
Sakanushi, K.2
Jin, L.3
Kajitani, Y.4
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11
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0030378255
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VLSI module placement based on rectangle-packing by the sequence-pair
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H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani, "VLSI Module Placement Based on Rectangle-packing by the Sequence-Pair", IEEE Trans, on CAD, Vol. 15, No. 12, pp. 1518-1524, 1996.
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(1996)
IEEE Trans, on CAD
, vol.15
, Issue.12
, pp. 1518-1524
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Murata, H.1
Fujiyoshi, K.2
Nakatake, S.3
Kajitani, Y.4
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12
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0030703004
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A mapping from sequence-pair to rectangular dissection
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H.Murata, K. Fujiyoshi, T. Watanabe, Y. Kajitani, "A Mapping from Sequence-Pair to Rectangular Dissection", ASP-DAC 1997, pp.625-634.
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ASP-DAC 1997
, pp. 625-634
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Murata, H.1
Fujiyoshi, K.2
Watanabe, T.3
Kajitani, Y.4
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13
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4344684112
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Selected sequence-pair: An efficient decode packing representation in linear time using sequence-pair
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C. Kodama, K. Fujiyoshi, "Selected Sequence-Pair: An Efficient Decode Packing Representation in Linear Time Using Sequence-Pair", ASP-DAC 2003,pp.331-337.
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ASP-DAC 2003
, pp. 331-337
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Kodama, C.1
Fujiyoshi, K.2
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14
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0034481271
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Corner block list: An efficient topological representation of non-slicing floorplan
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X. Hong, S. Dong, Y. Ma, Y. Cai, C. K. Cheng, and J. Gu, "Corner Block List: An Efficient Topological Representation of Non-Slicing Floorplan", ICCAD 2000, pp. 8-12
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ICCAD 2000
, pp. 8-12
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Hong, X.1
Dong, S.2
Ma, Y.3
Cai, Y.4
Cheng, C.K.5
Gu, J.6
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15
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0033701594
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B*-trees: A new representation for non-slicing floorplans
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LA, CA, June
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Y.-C. Chang, Y.-W. Chang, G.-M. Wu, and S.-W. Wu, "B*-trees: A New Representation for Non-Slicing Floorplans", 37th DAC, pp. 458-463, LA, CA, June 2000.
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(2000)
37th DAC
, pp. 458-463
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Chang, Y.-C.1
Chang, Y.-W.2
Wu, G.-M.3
Wu, S.-W.4
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16
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0034855935
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TCG: A transitive closure graph-based representation for non-slicing floorplans
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J.-M Lin and Y.-W Chang, "TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans", 38th DAC, pp.764-769, 2001
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(2001)
38th DAC
, pp. 764-769
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Lin, J.-M.1
Chang, Y.-W.2
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17
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85031277343
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Automatic floorplan design
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R.H.J.M. Otten, "Automatic Floorplan Design", 19th DAC, pp. 261-267, 1982
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(1982)
19th DAC
, pp. 261-267
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Otten, R.H.J.M.1
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18
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0032320385
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The channeled-BSG: A universal floorplan for simultaneous place/route with IC applications
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S.Nakatake, K. Sakanushi, Y. Kajitani, and M. Kawakita, "The Channeled-BSG: A Universal Floorplan for Simultaneous Place/Route with IC Applications",ICCAD 1998,pp. 418-425
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ICCAD 1998
, pp. 418-425
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Nakatake, S.1
Sakanushi, K.2
Kajitani, Y.3
Kawakita, M.4
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19
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0346148419
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Large-scale circuit placement: Gap and promise
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J. Cong, T. Kong, J. Shinnerl, M. Xie and X. Yuan, "Large-Scale Circuit Placement: Gap and Promise", IC-CAD 2003, pp.883-890
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IC-CAD 2003
, pp. 883-890
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Cong, J.1
Kong, T.2
Shinnerl, J.3
Xie, M.4
Yuan, X.5
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