A normalized configuration of floorplans and ABLR-relations

2004 International Conference on Communications, Circuits and Systems

Volumn 2, Issue , 2004, Pages 1218-1222

  Zhang, Xuliang ^a,b   Kajitani, Yoji ^b  

^a Jedat Innovation Inc   (Japan)

^b UNIVERSITY OF KITAKYUSHU   (Japan)

Author keywords

ABLR relation; Floorplan; Packing; Placement; Sequence pair; Single sequence; VLSI layout

Indexed keywords

ABLR-RELATION; FLOORPLAN; SEQUENCE-PAIR; SINGLE SEQUENCES; VLSI LAYOUT;

ALGORITHMS; DATA STRUCTURES; GEOMETRY; THEOREM PROVING; TOPOLOGY; TREES (MATHEMATICS); VLSI CIRCUITS;

INTEGRATED CIRCUIT LAYOUT;

EID: 11244302681     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)

1. Y. Kajitani, "The Single Sequence That Unifies Placement and Floorplanning", presented at the prosession meeting of ASP-DAC, 2003, "Asian Semi-Conductor University Cooperations", January, 2003.
2. S. Nakatake, K. Fujiyoshi, H. Murata and Y. Kajitani, "Module Placement on BSG-Structure and IC Layout Applications", ICCAD 1996, pp.484-451
3. K. Sakanushi, Y. Kajitani, and D. P. Mehta, "The Quarter-State-Sequence Floorplan Representation, IEEE Tractions On Circuits and Systems-I: Fundamental Theory and Applications", Vol. 50, No. 3, March 2003
4. Changwen, Y. Kajitani,"A New Floorplanning by HPG: Halmiton Path-based Graph Representation", ASICON 2003, pp. 174-177
5. M. Abe, "Covering The Square by Squares without Overlapping", Journal of Japan Mathematical Physics, Vol.4, No. 4, pp. 359-366, 1930 (in Japanese)
6. P. N. Guo, C. K. Cheng, and T. Yoshimura, "An O-Tree Representation of Non-Slicing Floorplan and Its Applications", 36th DAC, pp.286-291, Jun., 1999.
7. K. Sakanushi, K. Midorikawa, and Y. Kajitani, "A General and Fast Floorplaning by Reduct-Seq Representation", Technical Report of IEICE, (VLD2000-24), Vol.100, No.120, pp.109-116, 2000.
8. C. Zhuang, K. Sakanushi, L. Jin and Y. Kajitani, "An Enhanced Q-Sequence Augmented with Essential Empty Room Insertions and Parenthesis Trees", DATE 2002, pp.61-68
9. H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani, "VLSI Module Placement Based on Rectangle-packing by the Sequence-Pair", IEEE Trans. on CAD, Vol. 15, No. 12, pp. 1518-1524, 1996.
10. H.Murata, K. Fujiyoshi, T. Watanabe, Y. Kajitani, "A Mapping from Sequence-Pair to Rectangular Dissection", ASP-DAC 1997, pp.625-634.
11. C. Kodama, K. Fujiyoshi, "Selected Sequence-Pair: An Efficient Decode Packing Representation in Linear Time Using Sequence-Pair", ASP-DAC 2003,pp.331-337.
12. X. Hong, S. Dong, Y. Ma, Y. Cai, C. K. Cheng, and J. Gu, "Corner Block List: An Efficient Topological Representation of Non-Slicing Floorplan", ICCAD 2000, pp. 8-12
13. Y.-C. Chang, Y.-W. Chang, G.-M. Wu, and S.-W. Wu, "B*-trees: A New Representation for Non-Slicing Floorplans", 37th DAC, pp. 458-463, LA, CA, June 2000.
14. J.-M Lin and Y.-W Chang, "TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans", 38th DAC, pp.764-769, 2001
15. S.Nakatake, K. Sakanushi, Y. Kajitani, and M. Kawakita, "The Channeled-BSG: A Universal Floorplan for Simultaneous Place/Route with IC Applications",ICCAD 1998,pp. 418-425
16. X. Zhang, Y. Kajitani, X. Zhu, "Layer Based Area Partition Using Single-Sequence for Preferable Routes",Proc. ASICON 2003, pp.109-112
17. X. Zhang, Y. Kajitani, "Space-Planning: Placement of Modules with Controlled Empty Area by Single-Sequence", ASPDAC 2004, pp.25-30
18. X. Zhang, Y. Kajitani, "Theory of T-junction Floorplans in Terms of Single-Sequence", ISCAS 2004