The quarter-state-sequence floorplan representation

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

Volumn 50, Issue 3, 2003, Pages 376-386

  Sakanushi, Keishi ^a   Kajitani, Yoji ^b   Mehta, Dinesh P ^c  

^a OSAKA UNIVERSITY   (Japan)

^b UNIVERSITY OF KITAKYUSHU   (Japan)

^c Department of Geology and Geological Engineering   (United States)

Author keywords

Floorplan combinatorics; Floorplan representation; Graph theory; Q sequence; Simulated annealing

Indexed keywords

ALGORITHMS; CONSTRAINT THEORY; DATA STRUCTURES; DECODING; ENCODING (SYMBOLS); GRAPH THEORY; HEURISTIC METHODS; MATHEMATICAL TRANSFORMATIONS; PERTURBATION TECHNIQUES; SIMULATED ANNEALING;

FLOORPLAN COMBINATORICS; FLOORPLAN REPRESENTATION; QUARTER STATE SEQUENCE;

VLSI CIRCUITS;

EID: 0037667661     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2003.809442     Document Type: Article

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