Design of robust and high-performance 1-bit CMOS full adder for nanometer design

Proceedings - IEEE Computer Society Annual Symposium on VLSI: Trends in VLSI Technology and Design, ISVLSI 2008

Volumn , Issue , 2008, Pages 10-15

  Kavehei, Omid ^a   Azghadi, Mostafa Rahimi ^a   Navi, Keivan ^a   Mirbaha, Amir Pasha ^b  

^a SHAHID BEHESHTI UNIVERSITY   (Iran)

^b UNIVERSITÉ PARIS 1 PANTHÉON SORBONNE   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CHLORINE COMPOUNDS; CMOS INTEGRATED CIRCUITS; LOGIC CIRCUITS; LOGIC DESIGN; SWITCHING THEORY; TECHNOLOGY;

CELL-BASED DESIGNS; CMOS LOGIC; COMPLEX ARITHMETIC; CORE ELEMENTS; EASE-OF-USE; EXPONENTIATION; FULL ADDER; FULL ADDERS; NANO-METER SCALE; NANOMETER DESIGNS; NEW IDEAS; PARASITIC CAPACITORS; POST-LAYOUT SIMULATIONS; POWER CONSUMPTION; TRANSISTOR SCALING; VLSI TECHNOLOGIES;

ADDERS;

EID: 51849121136     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2008.16     Document Type: Conference Paper

References (13)

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