A novel reversible BCD adder or nanotechnology based systems

American Journal of Applied Sciences

Volumn 5, Issue 3, 2008, Pages 282-288

  Haghparast, Majid ^a   Navi, Keivan ^b  

^a ISLAMIC AZAD UNIVERSITY   (Iran)

^b SHAHID BEHESHTI UNIVERSITY   (Iran)

Author keywords

BCD adder; Full adder; Quantum computing; Reversible gate; Reversible logic

Indexed keywords

EID: 37348999037     PISSN: 15469239     EISSN: 15543641     Source Type: Journal    
DOI: 10.3844/ajassp.2008.282.288     Document Type: Article

References (20)

1. Landauer R., 1961. Irreversibility and heat generation in the computing process. IBM J. Research and Development, 5(3): 183-191.
2. Bennett C. H., 1973. Logical reversibility of computation. IBM J. Research and Development, 17: 525-532.
3. Hayes B., 2006. Reverse engineering. American Scientist, 94: 107-111.
4. Vasudevan D. P., P. K. Lala and J. P. Parkerson, 2004. Online testable reversible logic circuit design using NAND blocks. Proc. Symposium on Defect and Fault Tolerance, pp. 324-331.
5. Parhami B., 2006. Fault tolerant reversible circuits. Proc. 40th Asilomar Conf. Signals, Systems, and Computers, October 2006, Pacific Grove, CA.
6. Perkowski M., A. Al-Rabadi, P. Kerntopf, A. Buller, M. Chrzanowska-Jeske, A. Mishchenko, M. Azad Khan, A. Coppola, S. Yanushkevich, V. Shmerko and L. Jozwiak, 2001. A general decomposition for reversible logic, Proc. RM 2001, Starkville, pp. 119-138.
7. Perkowski M and P Kerntopf, 2001. Reversible Logic. Invited tutorial, Proc. EURO-MICRO, Sept 2001, Warsaw, Poland.
8. Thapliyal Himanshu and M. B. Srinivas, 2005. Novel reversible TSG gate and its application for designing reversible carry look ahead adder and other adder architectures. Proceedings of the 10h Asia-Pacific Computer Systems Architecture Conference (ACSAC 05), Lecture Notes of Computer Science, 3740: 775-786. Springer-Verlag.
9. Thaphyal H., S. Kotiyal, M. B. Srinivas, 2006. Novel BCD adders and their reversible logic implementation for IEEE 754r format. Proceedings of the 19th International Conference on VLSI Design, 3-7 Jan 2006.
10. Feynman R., 1985. Quantum mechanical computers. Optics News, 11: 11-20.
11. Toffoli T., 1980. Reversible computing. Tech Memo MIT/LCS/TM-151, MIT Lab for Computer Science.
12. Fredkin E. and T. Toffoli, 1982. Conservative logic. Int'l J. Theoretical Physics, 21: 219-253.
13. Azad Khan Md. M. H., 2002. Design of full adder with reversible gate. International Conference on Computer and Information Technology, Dhaka, Bangladesh, pp. 515-519.
14. Hasan Babu Hafiz Md. and Ahsan Raja Chowdhury, 2005. Design of a reversible binary coded decimal adder by using reversible 4-bit parallel adder. VLSI Design 2005, Kolkata, India, pp. 255-260.
15. Peres A., 1985. Reversible logic and quantum computers. Physical Review. A 32: 3266-3276.
16. Hasan Babu Hafiz Md., Md. Rafiqul Islam, Ahsan Raja Chowdhury and Syed Mostahed Ali Chowdhury, 2003. On the realization of reversible full adder circuit. International Conference on Computer and Information Technologyj Dhaka, Bangladesh, 2: 880-883.
17. Hasan Babu Hafiz Md. Md. Rafiqul Islam, Syed Mostahed Ali Chowdhury and Ahsan Raja Chowdbury, 2003. Reversible iogic synthesis for minimizzition of full adder circuit. Proceeding of the EuroMicro Symposium on Digital System Design (DSD 03), Belek Antalya, Turkey, pp. 50-54.
18. Hasan Babu Hafiz Md., Md. Rafiqul Islam, Syed Mostahed Ali Chowdhury and Ahsan Raja Chowdhury, 2004. Synthesis of full adder circuit using reversible logic. Proceedings 17th International Conference on VLSI Design (VLSI Design 2004), Mumbai, India, pp. 757-760.
19. Bruce J. W., M. A. Thornton, L. Shivakumariah, P. S. Kokate and X. Li, 2002. Efficient adder circuits based on a conservative logic gate. Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 02), April 2002, Pittsburgh, PA, USA, pp. 83-88.
20. Khlopotine A., M. Perkowski and P. Kerntopf, 2002. Reversible logic synthesis by gate composition. Proceedings of IWLS 2002, pp. 261-266.