Performance evaluation of 1-bit CMOS adder cells

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 1999, Pages

  Shams, A ^a   Bayoumi, M ^a  

^a UNIVERSITY OF LOUISIANA AT LAFAYETTE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC VARIABLES MEASUREMENT; ENERGY DISSIPATION; ENERGY UTILIZATION; PERFORMANCE;

ADDER CELLS; CORRECT FUNCTIONALITY; INPUT TEST PATTERN; POWER CONSUMPTION MEASUREMENT; POWER DISSIPATION; TIME DELAY;

INTEGRATED CIRCUIT TESTING;

EID: 0032692520     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (12)