Mitigating Inductive Noise in SMT Processors

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn 2004-January, Issue January, 2004, Pages 332-337

  El Essawy, Wael ^a   Albonesi, David H ^a  

^a University of Rochester   (United States)

Author keywords

clock gating; inductive noise; power delivery; SMT

Indexed keywords

ELECTRIC POWER TRANSMISSION; LOW POWER ELECTRONICS; MICROPROCESSOR CHIPS; NOISE POLLUTION; SURFACE MOUNT TECHNOLOGY;

CLOCK GATING; CURRENT FLUCTUATIONS; INDUCTIVE NOISE; MICROARCHITECTURAL SIMULATION; MULTIPLE THREADS; PERFORMANCE ENHANCEMENTS; POWER DELIVERY; SIMULTANEOUS MULTI-THREADING;

POWER ELECTRONICS;

EID: 84932172811     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/LPE.2004.241160     Document Type: Conference Paper

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