Implications of device timing variability on full chip timing

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2007, Pages 37-45

  Annavaram, Murali ^a   Grochowski, Ed ^a   Reed, Paul ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DUO MICROPROCESSOR DESIGN; FUNCTIONAL BLOCK TIMING;

MICROPROCESSOR CHIPS; PARAMETER ESTIMATION; PROBABILITY DISTRIBUTIONS;

SCHEDULING;

EID: 34547676261     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2007.346183     Document Type: Conference Paper

References (16)

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