Self-checking instructions - Reducing instruction redundancy for concurrent error detection

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn 2006, Issue , 2006, Pages 64-73

  Kumar, Sumeet ^a   Aggarwal, Aneesh ^a  

^a State University of New York at Binghamton   (United States)

Author keywords

Concurrent error detection; Reducing instruction redundancy; Redundant multi threading; Self checking instructions

Indexed keywords

CONCURRENT ERROR DETECTION; REDUCING INSTRUCTION REDUNDANCY; REDUNDANT MULTI THREADING (RMT); REDUNDANT MULTITHREADING; SELF CHECKING INSTRUCTIONS;

CODES (SYMBOLS); COMPUTER ARCHITECTURE; CONCURRENT ENGINEERING; ENERGY UTILIZATION; ERROR ANALYSIS; MICROPROCESSOR CHIPS;

ERROR DETECTION;

EID: 34247100370     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1152154.1152168     Document Type: Conference Paper

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