A low-power motion estimation block for low bit-rate wireless video

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 2001, Pages 60-63

  Richmond II, S R ^a   Dong Sam Ha, ^a  

^a HEWLETT PACKARD COMPANY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BIT ERROR RATE; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; ENERGY DISSIPATION; ENERGY UTILIZATION; IMAGE CODING; MICROPROCESSOR CHIPS; MOBILE RADIO SYSTEMS; MOTION ESTIMATION;

LOW BIT-RATE; WIRELESS VIDEO;

VIDEO TELEPHONE EQUIPMENT;

EID: 0034871150     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. A new architecture for computationally adaptive full-search block-matching motion estimation
2. Motion-compensated interframe coding for video conferencing
3. A novel four-step search algorithm for fast block motion estimation
4. A VLSI architecture for hierarchical motion estimation