An overview of low-power techniques for field-programmable gate arrays

Proceedings of the 2008 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2008

Volumn , Issue , 2008, Pages 338-345

  Lamoureux, Julien ^a   Luk, Wayne ^a  

^a IMPERIAL COLLEGE LONDON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER-AIDED DESIGN; ENERGY CONSUMPTION; FIELD-PROGRAMMABLE GATE ARRAYS; FUTURE WORK; LEVEL DESIGN; LOW POWERS; LOW-POWER TECHNIQUES; SYSTEM-LEVEL DESIGNS;

ADAPTIVE SYSTEMS; DESIGN; ENERGY POLICY; LOGIC GATES; MOBILE DEVICES; REAL TIME SYSTEMS; TELECOMMUNICATION EQUIPMENT;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 51949090843     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/AHS.2008.71     Document Type: Conference Paper

References (67)

1. Actel, "IGLOO Handbook," 2008.
2. Altera, "Quartus II Handbook," Vol. 2, Chapter 9, 2007.
3. Altera, "Quartus II Handbook," Vol. 3, Chapter 10, 2007.
4. Altera Corp., "Cut power 100X using CPLD coprocessors in Portable Applications," Webcast, Dec. 2007.
5. M.J. Alexander, "Power optimization for FPGA look-up tables," Proc. ACM Int. Symp. on Physical Design, pp. 156-162, 1997.
6. J.H. Anderson and F.N. Najm, "Power-aware technology mapping for LUT-based FPGAs," Proc. IEEE Int. Conference on Field-Prog. Technology, pp. 211-218, 2002.
7. J.H. Anderson and F.N. Najm, "A novel low-power FPGA routing switch," Proc. IEEE Custom Integrated Circuits Conf., pp. 719-722, 2004.
8. J.H. Anderson, F.N. Najm, and T. Tuan, "Active leakage power optimization for FPGAs," IEEE Trans. on Computer-Aided Design, vol. 25, no. 3, pp. 423-437, March 2006.
9. V. Betz., J. Rose, and A. Marquardt, "Architecture and CAD for deep-submicron FPGAs," Kluwer Academic Publishers, 1999.
10. P. Biswas et al, "Performance and energy benefits of instruction set extensions in an FPGA soft core," Proc. Int. Conf. on VLSI Design, pp. 651-656, 2006.
11. D. Chen and J. Cong, "Delay optimal low-power circuit clustering for FPGAs with dual supply voltages," Proc. Int. Symp. on Low Power Electronics and Design, pp. 70-73, 2004.
12. D. Chen, J. Cong, and Y. Fan, "Low-power high-level synthesis for FPGA architecture," Low Power Electronics and Design, pp. 134-139, 2003.
13. D. Chen, J. Cong, Y. Fan, and Z. Zhang, "High-level power estimation and low-power design space exploration for FPGAs," Proc. Asia South Pacific Design Automation Conf., pp. 529-534, 2007.
14. D. Chen, J. Cong, F. Li, and L. He, "Low-power technology mapping for FPGA architectures with dual supply voltages," Proc. ACM Int. Symp. on Field-Prog. Gate Arrays, pp. 109-117, 2004.
15. D. Chen, J. Cong, and J. Xu, "Optimal module and voltage assignment for low-power," Proc. Asia South Pacific Design Automation Conf., pp. 850-855, 2005.
16. C.T. Chow et al, "Dynamic voltage scaling for commercial FPGAs," Proc. IEEE Int. Conf. on Field Prog. Technology, 2005.
17. G. Constantinides, "Word-length optimization for differentiable nonlinear systems," ACM Trans. on Design Automation of Electronic Sys., vol. 11, no. 1, pp. 26-43, 2006.
18. R. Dimond, O. Mencer and W. Luk, "Combining instruction coding and scheduling to optimize energy in system-on-FPGA," Proc. IEEE Symp. on Field-Prog. Custom Computing Machines, IEEE Computer Society Press, 2006.
19. A.H. Farrahi and M. Sarrafzadeh, "FPGA technology mapping for power minimization," Proc. Int. Workshop on Field-Prog. Logic and Applications, pp. 167-174, 1994.
20. B.H. Fetcher, "FPGA embedded processors: revealing true system performance," Proc. Embedded Sys. Conf., ETP-357, 2005.
21. V. George, H. Zhang, and J. Rabaey, "The design of a low energy FPGA," Proc. Int. Symp. on Low Power Electronics and Design, pp. 188-193, 1999.
22. K. Glette, J. Torresen and M. Yasunaga, "Online evaluation for a high-speed image recognition system implemented on a Virtex-II Pro FPGA," Proc. NASA/ESA Conf. on Adaptive Hardware and Sys., pp. 463-470, IEEE, 2007.
23. H. Hassan, M. Anis, A. El Daher, and M. Elmasry, "Activity packing in FPGAs for leakage power reduction," Proc. Design Automation and Test in Europe, pp. 212-217, 2005.
24. International Technology Roadmap for Semiconductors, 2005.
25. T. Jiang, X. Tang, and P. Banerjee, "Macro-models for high level area and power estimation on FPGAs," Proc. ACM Great Lakes Symp. on VLSI, pp. 162-165, 2004.
26. B. Kapoor, "Improving the accuracy of circuit activity measurement," Proc. ACM Design Automation Conf., pp. 734-739, 1994.
27. S. Khawam et al, "The reconfigurable instruction cell array," IEEE Trans. on VLSI Sys., vol. 16, no. 1, pp. 75-85, 2008.
28. B. Kumthekar, and F. Somenzi, "Power and delay reduction via simultaneous logic and placement optimization in FPGAs," Proc. Design Automation and Test in Europe, pp. 202-207, 2000.
29. I. Kuon and J. Rose, "Measuring the gap between FPGAs and ASICs," IEEE Trans. on Computer-Aided Design, vol. 26, no. 2, pp. 203-215, Feb. 2007.
30. E. Kusse and J. Rabaey, "Low-energy embedded FPGA structures," Proc. Int. Symp. Low Power Electronics and Design, pp. 155-160, 1999.
31. J. Lamoureux and S.J.E. Wilton, "On the Interaction between Power-Aware CAD Algorithms for FPGAs," Proc. IEEE Int. Conf. on Computer Aided Design, pp. 701-708, 2003.
32. J. Lamoureux and S.J.E. Wilton, "Activity estimation for Field-Programmable Gate Arrays," Proc. Intl. Conf. on Field-Prog. Logic and Applications, pp. 87-94, 2006.
33. J. Lamoureux, G.G. Lemieux, and S.J.E. Wilton, "GlitchLess: dynamic power minimization in FPGAs through edge alignment and glitch filtering," to appear in IEEE Trans. on Very Large Scale Integration Systems, 2008.
34. J. Lamoureux and S.J.E. Wilton, "FPGA clock network architecture: flexibility vs. area and power," Proc. ACM Int. Symp. on Field-Prog. Gate Arrays, pp. 101-108, 2006.
35. J. Lamoureux and S.J.E. Wilton, "Clock-aware placement for FPGAs," Proc. Int. Conf. on Field-Prog. Logic and Applications, pp. 124-131, 2007.
36. F. Li, D. Chen, L. He, and J. Cong, "Architecture evaluation for power-efficient FPGAs," Proc. ACM Int. Symp. on Field-Programmable Gate Arrays, pp. 175-184, 2003.
37. F. Li, Y. Lin, and L. He, "FPGA power reduction using configurable dual-Vdd," Proc. Design Automation Conf., pp. 735-740, 2004.
38. F. Li, Y. Lin, L. He, and J. Cong, "Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics," Proc. ACM Int. Symp. on Field-Prog. Gate Arrays, pp. 42-50, 2004.
39. H. Li, S. Katkoori, and W.-K. Mak, "Power minimization algorithms for LUT-based FPGA technology mapping," ACM Trans. on Design Automation of Electronic Sys., vol. 9, no. 1, pp. 33-51, 2004.
40. J, Liang, R. Tessier and D. Goeckel, "A dynamically reconfigurable power efficient turbo coder," Proc. IEEE Symp. on Field-Prog. Custom Computing Machines, IEEE Computer Society Press, pp. 91-100, 2004.
41. Y. Lin, F. Li, and L. He, "Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction," Proc. Asia South Pacific Design Automation Conf., pp. 645-650, 2005.
42. R. Marculescu, D. Marculescu, and M. Pedram, "Switching activity analysis considering spatiotemporal correlations," Proc. IEEE Int. Conf. Computer-Aided Design, pp. 294-299, 1994.
43. M. Meijer, R. Krishnan, and M. Bennebroek, "Energy efficient FPGA interconnect design," Proc. Conf. on Design and Test in Europe, pp. 1-6, 2006.
44. J. Monteiro and S. Devadas, "A methodology for efficient estimation of switching activity in sequential logic circuits," Proc. ACM/IEEE Design Automation Conf., pp. 12-17, 1994.
45. F. Najm, "Low-pass filter for computing the transition density in digital circuits," IEEE Trans. on Computer-Aided Design, vol. 13, no. 9, pp. 1123-1131, 1994.
46. J. Noguera and I.O. Kennedy, "Power reduction in network equipment through adaptive partial reconfiguration," Proc. Int. Conf. on Field Prog. Logic and Applications, IEEE, pp. 240-245, 2007.
47. W.G. Osborne, W. Luk, J.G.F. Coutinho and O. Mencer, "Power and branch aware word-length optimisation," Proc. IEEE Symp. on Field-Prog. Custom Computing Machines, IEEE Computer Society Press, 2008.
48. W.G. Osborne, W. Luk, J.G.F. Coutinho and O. Mencer, "Reconfigurable design with clock gating," Proc. Int. Symp. on Systems, Architectures, Modelling and Simulation, 2008.
49. K. Paulsson, M. Hubner and J. Becker, "Strategies to on-line failure recovery in self-adaptive systems based on dynamic and partial reconfiguration," Proc. NASA/ESA Conf. on Adaptive Hardware and Sys., IEEE, pp. 288-291, 2006.
50. K.K.W. Poon, S.J.E. Wilton, and A. Yan, "A detailed power model for field-programmable gate arrays," ACM Trans. on Design Automation of Electronic Systems, vol. 10, no. 2, pp. 279-302, April 2005.
51. A. Raghunathan, S. Dey and N. K. Jia, "Register transfer level power optimization with emphasis on glitch analysis and reduction," IEEE Trans.on Computer-Aided Design, vol. 18, no. 8, pp. 1114-1131, 1999.
52. A. Reimer, A. Schulz, and W. Nebel, "Modeling macromodules for high-level dynamic power estimation of FPGA-based digital designs," Proc. Int. Symp. on Low Power Electronics and Design, pp. 151-154, 2006.
53. K. Roy, "Power-dissipation driven FPGA place and route under timing constraints," IEEE Trans. on Circuits and Sys., vol. 46, no. 5, pp. 634-637, 1999.
54. A. Singh, G. Parthasarathy, and M. Marek-Sadowski, "Efficient circuit clustering for area and power reduction in FPGAs," ACM Trans. on Design Automation of Electronic Systems, vol. 7, no. 4, pp. 643-663, 2002.
55. S. Sivaswamy, G. Wang, C. Ababei, K. Bazargan, R. Kastner, and E. Bozargzadeh, "HARP: hard-wired routing pattern FPGAs," Proc. Int. Symp. on Field-Prog. Gate Arrays, pp. 21-29, 2005.
56. R. Tessier, V. Betz, D. Neto, A. Egier, and T. Gopalsamy, "Power-Efficient RAM mapping algorithms for FPGA embedded memory blocks," IEEE Trans. of Computer- Aided Design, vol. 26, no. 2, pp. 278-289, Feb 2007.
57. N. Togawa et al, "A simultaneous placement and global routing algorithm for FPGAs with power optimization," Proc. Asia Pacific Conf. on Circuits and Sys., pp. 125-128, 1998.
58. J. Torresen and J. Jakobsen, "An FPGA-implemented processor architecture with adaptive resolution," Proc. NASA/ESA Conf. on Adaptive Hardware and Sys., IEEE, pp. 386-389, 2006.
59. C.Y. Tsui et al, "Exact and approximate methods for calculating signal and transition probabilities in FSMs," Proc. ACM/IEEE Design Automation Conf., pp. 18-23, 1994.
60. C.Y. Tsui, M. Pedram, and A.M Despain, "Efficient estimation of dynamic power consumption under a real delay model," Proc. IEEE Int. Conf. Computer-Aided Design, pp. 224-228, 1993.
61. T. Tuan, A. Rahman, S. Das, S. Trimberger, and S. Kao, "A 90-nm low-power FPGA for battery-powered applications," IEEE Trans. on Computer-Aided Design, vol. 26, no. 2, pp. 296-300, Feb. 2007.
62. A. Upegui and E. Sanchez, "Evolving hardware with self-configurable connectivity in Xilinx FPGAs," Proc. NASA/ESA Conf. on Adaptive Hardware and Sys., IEEE, pp. 153-162, 2006.
63. C-C. Wang and C-P Kwan, "Low power technology mapping by hiding high-transition paths in invisible edges for LUT-based FPGAs," Proc. IEEE Int. Symp. on Circuits and Sys., pp. 1536-1539, 1997.
64. Z-H. Wang, E-C. Liu, J. Lai, and T-C. Wang, "Power minimization in LUT-based FPGA technology mapping," Proc. ACM Asia South Pacific Design Automation Conf., pp. 635-640, 2001.
65. S.J.E. Wilton, S-S. Ang, and W. Luk. "The impact of pipelining on energy per operation in field programmable gate arrays". In Proc. Field Prog. Logic and Applications, LNCS 3203, pp. 719-728, 2004.
66. Xilinx, "Optimizing FPGA power with ISE design tools," Xcell Journal, Issue 60, pp. 16-19, 2007.
67. Xilinx, "Power Consumption in 65nm FPGAs," 2007.