-
1
-
-
0033726476
-
Glitch power minimization by selective gate freezing
-
L. Benini et al, Glitch power minimization by selective gate freezing, IEEE Trans. VLSI Systems, 8(3): 287-298, 2000.
-
(2000)
IEEE Trans. VLSI Systems
, vol.8
, Issue.3
, pp. 287-298
-
-
Benini, L.1
-
2
-
-
84947927239
-
Some notes on power management on FPGA based systems
-
Field Programmable Logic and Applciations, Springer
-
E. I. Boemo et al, Some notes on power management on FPGA based systems, Field Programmable Logic and Applciations, LNCS 975, Springer, 1995, pp. 149-157.
-
(1995)
LNCS
, vol.975
, pp. 149-157
-
-
Boemo, E.I.1
-
3
-
-
35048872506
-
Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs
-
N. Chabini et al, Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs, Proc. ACM Great Lakes Symposium on VLSI, 2003.
-
(2003)
Proc. ACM Great Lakes Symposium on VLSI
-
-
Chabini, N.1
-
4
-
-
0346675185
-
A complete model for glitch analysis in logic circuits
-
K. S. Chung, T. Kim and C. L. Liu, A complete model for glitch analysis in logic circuits. Journal of Circuits, Systems, and Computers, 11(2): 137-154, 2002.
-
(2002)
Journal of Circuits, Systems, and Computers
, vol.11
, Issue.2
, pp. 137-154
-
-
Chung, K.S.1
Kim, T.2
Liu, C.L.3
-
7
-
-
0035704561
-
Influence of compiler optimizations on system power
-
M. Kandemir et al, Influence of compiler optimizations on system power, IEEE Trans. VLSI, 9(6):801-804, 2001.
-
(2001)
IEEE Trans. VLSI
, vol.9
, Issue.6
, pp. 801-804
-
-
Kandemir, M.1
-
9
-
-
0034187956
-
Power optimization of FPGA-based designs without rewiring
-
B. Kumthekar et al, Power optimization of FPGA-based designs without rewiring, IEE Proc., 147(3): 167-174, 2002.
-
(2002)
IEE Proc.
, vol.147
, Issue.3
, pp. 167-174
-
-
Kumthekar, B.1
-
10
-
-
0346148417
-
On the interaction between power-aware FPGA CAD algorithms
-
J. Lamoureux and S. Wilton, On the interaction between power-aware FPGA CAD algorithms, Proc. ICCAD, 2003.
-
(2003)
Proc. ICCAD
-
-
Lamoureux, J.1
Wilton, S.2
-
11
-
-
0035410679
-
Parameterized hardware libraries for configurable system-on-chip technology
-
W. Luk et al. Parameterized hardware libraries for configurable system-on-chip technology, Canadian Journal of Elect. and Computer Engineering, 26(3/4):125-129, 2001.
-
(2001)
Canadian Journal of Elect. and Computer Engineering
, vol.26
, Issue.3-4
, pp. 125-129
-
-
Luk, W.1
-
13
-
-
0027799710
-
Retiming sequential circuits for low power
-
J. C. Monteiro, S. Devadas and A. Ghosh, Retiming sequential circuits for low power, Proc. ICCAD, pp. 398-402, 1993.
-
(1993)
Proc. ICCAD
, pp. 398-402
-
-
Monteiro, J.C.1
Devadas, S.2
Ghosh, A.3
-
15
-
-
0032668489
-
Register transfer level power optimization with emphasis on glitch analysis and reduction
-
A. Raghunathan, S. Dey and N. K. Jia, Register transfer level power optimization with emphasis on glitch analysis and reduction, IEEE Trans. CAD, 18(8):114-1131, 1999.
-
(1999)
IEEE Trans. CAD
, vol.18
, Issue.8
, pp. 114-1131
-
-
Raghunathan, A.1
Dey, S.2
Jia, N.K.3
-
16
-
-
85087228718
-
A hardware/software co-design flow and IP library based on Simulink
-
L. M. Reyneri et al, A hardware/software co-design flow and IP library based on Simulink, Proc. 38th Design Automation Conference, 2001.
-
(2001)
Proc. 38th Design Automation Conference
-
-
Reyneri, L.M.1
-
17
-
-
0035019250
-
Interconnect pipelining in a throughput-intensive FPGA architecture
-
A. Singh et al. Interconnect pipelining in a throughput-intensive FPGA architecture, ACM/SIGDA Int. Symp. on Field-Programmable Gate Arrays, 2001, pp 153-160.
-
(2001)
ACM/SIGDA Int. Symp. on Field-Programmable Gate Arrays
, pp. 153-160
-
-
Singh, A.1
-
19
-
-
33746055852
-
Using on-chip configurable logic to reduce embedded system software energy
-
IEEE Computer Society Press
-
G. Stitt et al, Using on-chip configurable logic to reduce embedded system software energy, Proc. Int. Symp. Field-Programmable Custom Computing Machines, IEEE Computer Society Press, 2002, pp. 143-151.
-
(2002)
Proc. Int. Symp. Field-Programmable Custom Computing Machines
, pp. 143-151
-
-
Stitt, G.1
-
20
-
-
35048900821
-
Logic depth, power, and pipeline granularity: Updated results on XC4K and Virtex FPGAs
-
Publicaciones Digitales S.A.
-
G. Sutter et al, Logic depth, power, and pipeline granularity: updated results on XC4K and Virtex FPGAs, Computacion Reconfigurable & FPGAs, Publicaciones Digitales S.A., 2003, pp. 201-207.
-
(2003)
Computacion Reconfigurable & FPGAs
, pp. 201-207
-
-
Sutter, G.1
-
22
-
-
0036907308
-
A hybrid ASIC and FPGA architecture
-
P. Zuchowski et al, A hybrid ASIC and FPGA architecture, Proc. ICCAD, 2002, pp. 187-194.
-
(2002)
Proc. ICCAD
, pp. 187-194
-
-
Zuchowski, P.1
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