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Volumn , Issue , 2007, Pages 240-245

Power reduction in network equipment through adaptive partial reconfiguration

Author keywords

[No Author keywords available]

Indexed keywords

DECODING; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); LAWS AND LEGISLATION; VITERBI ALGORITHM;

EID: 48149091080     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2007.4380654     Document Type: Conference Paper
Times cited : (40)

References (7)
  • 1
    • 48149102328 scopus 로고    scopus 로고
    • Becker, J., Hübner, M., Ullmann, M., Power Estimation and Power Mesurement of Xilinx Virtex FPGAs: Trade-offs and Limitations, SBCCI 03
    • Becker, J., Hübner, M., Ullmann, M., "Power Estimation and Power Mesurement of Xilinx Virtex FPGAs: Trade-offs and Limitations", SBCCI 03
  • 3
    • 84922684224 scopus 로고    scopus 로고
    • Enhanced architectures, design methodologies and CAD tools for dynamic reconfiguration on Xilinx FPGAs
    • Lysaght, P. et al "Enhanced architectures, design methodologies and CAD tools for dynamic reconfiguration on Xilinx FPGAs". In Proceedings of FPL'06.
    • Proceedings of FPL'06
    • Lysaght, P.1
  • 6
  • 7
    • 48149107197 scopus 로고    scopus 로고
    • The Impact of Pipelining on Energy per Operation in FPGAs
    • Wilton, S. et al., "The Impact of Pipelining on Energy per Operation in FPGAs". In Proceedings of FPL'04.
    • Proceedings of FPL'04
    • Wilton, S.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.